X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fdm355evm.cfg;h=bf5659cccb0c8998466c520e8d0805bae07ea8c2;hb=d47aaf6d92788efc90c6d3379d58132e7ddfa781;hp=9b32ef9e2e573167124b6ea00d1cc3c692f71d26;hpb=6d08c1800c7d313c3e6be9fe2c7124df02749665;p=fw%2Fopenocd

diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 9b32ef9e2..bf5659ccc 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-init { dm355evm_init }
 proc dm355evm_init {} {
 	global dm355
 
-	puts "Initialize DM355 EVM board"
+	echo "Initialize DM355 EVM board"
 
 	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
 	jtag_rclk 1500
@@ -35,7 +35,7 @@ proc dm355evm_init {} {
 	set addr [dict get $dm355 pllc1]
 	set pll_divs [dict create]
 	dict set pll_divs div3 16
-	dict set pll_divs div4 8
+	dict set pll_divs div4 4
 	pll_v02_setup $addr 144 $pll_divs
 
 	# ARM is now running at 216 MHz, so JTAG can go faster
@@ -48,6 +48,7 @@ proc dm355evm_init {} {
 
 	set addr [dict get $dm355 pllc2]
 	set pll_divs [dict create]
+	dict set pll_divs div1 1
 	dict set pll_divs prediv 8
 	pll_v02_setup $addr 114 $pll_divs
 
@@ -77,7 +78,54 @@ proc dm355evm_init {} {
 	########################
 	# DDR2 EMIF
 
-	# FIXME setup
+	# VTPIOCR impedance calibration
+	set addr [dict get $dm355 sysbase]
+	set addr [expr {$addr + 0x70}]
+
+	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
+	mmw $addr 0 0x20c0
+	mmw $addr 0x2000 0
+
+	# wait for READY
+        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
+
+	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
+	mmw $addr 0x4000 0
+	mmw $addr 0x0180 0
+	mmw $addr 0x0040 0
+
+	# NOTE:  this DDR2 initialization sequence borrows from
+	# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+	# reset (then re-enable) DDR controller
+	psc_reset 13
+	psc_go
+	psc_enable 13
+	psc_go
+
+	# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+	set addr [dict get $dm355 ddr_emif]
+
+	# DDRPHYCR1
+	mww [expr {$addr + 0xe4}] 0x50006404
+
+	# PBBPR -- burst priority
+	mww [expr {$addr + 0x20}] 0xfe
+
+	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
+
+	# SDTIMR0, SDTIMR1
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
+
+	# SDCR -- relock SDTIM*
+	mmw [expr {$addr + 0x08}] 0 0x00008000
+
+	# SDRCR -- refresh rate (171 MHz * 7.8usec)
+	mww [expr {$addr + 0x0c}] 1336
 
 	########################
 	# ASYNC EMIF
@@ -90,18 +138,51 @@ proc dm355evm_init {} {
 	#set nand_timings 0x0400008c
 
 	# AWCCR
-	mww [expr $addr + 0x04] 0xff
+	mww [expr {$addr + 0x04}] 0xff
 	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
-	mww [expr $addr + 0x10] $nand_timings
+	mww [expr {$addr + 0x10}] $nand_timings
 	# CS1 == dm9000 Ethernet
-	mww [expr $addr + 0x14] 0x00a00505
+	mww [expr {$addr + 0x14}] 0x00a00505
 	# NANDFCR -- only CS0 has NAND
-	mww [expr $addr + 0x60] 0x01
+	mww [expr {$addr + 0x60}] 0x01
+
+	# default: both chipselects to the NAND socket are used
+	nand probe 0
+	nand probe 1
 
 	########################
 	# UART0
 
-	# FIXME setup
+	set addr [dict get $dm355 uart0]
+
+	# PWREMU_MGNT -- rx + tx in reset
+	mww [expr {$addr + 0x30}] 0
+
+	# DLL, DLH -- 115200 baud
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
+
+	# FCR - clear and disable FIFOs
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
+
+	# IER - disable IRQs
+	mwb [expr {$addr + 0x04}] 0x00
+
+	# LCR - 8-N-1
+	mwb [expr {$addr + 0x0c}] 0x03
+
+	# MCR - no flow control or loopback
+	mwb [expr {$addr + 0x10}] 0x00
+
+	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
+	mww [expr {$addr + 0x30}] 0xe001
+
+
+	########################
+
+	# turn on icache - set I bit in cp15 register c1
+	arm mcr 15 0 0 1 0 0x00051078
 }
 
 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
@@ -110,8 +191,10 @@ proc dm355evm_init {} {
 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-nand device davinci 0 0x02000000 hwecc4 0x01e10000
-nand device davinci 0 0x02004000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.boot
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
 
 # FIXME
 #  - support writing UBL with its header (new layout only with new ROMs)