X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fdm355evm.cfg;h=bf5659cccb0c8998466c520e8d0805bae07ea8c2;hb=d47aaf6d92788efc90c6d3379d58132e7ddfa781;hp=0c971e9a0b06bc248614b718a9300270857fd58c;hpb=e7b2958229c7e0d7e98e130764aa50d1ca9017d3;p=fw%2Fopenocd

diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 0c971e9a0..bf5659ccc 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -80,14 +80,14 @@ proc dm355evm_init {} {
 
 	# VTPIOCR impedance calibration
 	set addr [dict get $dm355 sysbase]
-	set addr [expr $addr + 0x70]
+	set addr [expr {$addr + 0x70}]
 
 	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
 	mmw $addr 0 0x20c0
 	mmw $addr 0x2000 0
 
 	# wait for READY
-        while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
+        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
 
 	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
 	mmw $addr 0x4000 0
@@ -108,24 +108,24 @@ proc dm355evm_init {} {
 	set addr [dict get $dm355 ddr_emif]
 
 	# DDRPHYCR1
-	mww [expr $addr + 0xe4] 0x50006404
+	mww [expr {$addr + 0xe4}] 0x50006404
 
 	# PBBPR -- burst priority
-	mww [expr $addr + 0x20] 0xfe
+	mww [expr {$addr + 0x20}] 0xfe
 
 	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
-	mmw [expr $addr + 0x08] 0x00800000 0
-	mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
 
 	# SDTIMR0, SDTIMR1
-	mww [expr $addr + 0x10] 0x2a923249
-	mww [expr $addr + 0x14] 0x4c17c763
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
 
 	# SDCR -- relock SDTIM*
-	mmw [expr $addr + 0x08] 0 0x00008000
+	mmw [expr {$addr + 0x08}] 0 0x00008000
 
 	# SDRCR -- refresh rate (171 MHz * 7.8usec)
-	mww [expr $addr + 0x0c] 1336
+	mww [expr {$addr + 0x0c}] 1336
 
 	########################
 	# ASYNC EMIF
@@ -138,13 +138,13 @@ proc dm355evm_init {} {
 	#set nand_timings 0x0400008c
 
 	# AWCCR
-	mww [expr $addr + 0x04] 0xff
+	mww [expr {$addr + 0x04}] 0xff
 	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
-	mww [expr $addr + 0x10] $nand_timings
+	mww [expr {$addr + 0x10}] $nand_timings
 	# CS1 == dm9000 Ethernet
-	mww [expr $addr + 0x14] 0x00a00505
+	mww [expr {$addr + 0x14}] 0x00a00505
 	# NANDFCR -- only CS0 has NAND
-	mww [expr $addr + 0x60] 0x01
+	mww [expr {$addr + 0x60}] 0x01
 
 	# default: both chipselects to the NAND socket are used
 	nand probe 0
@@ -156,27 +156,27 @@ proc dm355evm_init {} {
 	set addr [dict get $dm355 uart0]
 
 	# PWREMU_MGNT -- rx + tx in reset
-	mww [expr $addr + 0x30] 0
+	mww [expr {$addr + 0x30}] 0
 
 	# DLL, DLH -- 115200 baud
-	mwb [expr $addr + 0x20] 0x0d
-	mwb [expr $addr + 0x24] 0x00
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
 
 	# FCR - clear and disable FIFOs
-	mwb [expr $addr + 0x08] 0x07
-	mwb [expr $addr + 0x08] 0x00
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
 
 	# IER - disable IRQs
-	mwb [expr $addr + 0x04] 0x00
+	mwb [expr {$addr + 0x04}] 0x00
 
 	# LCR - 8-N-1
-	mwb [expr $addr + 0x0c] 0x03
+	mwb [expr {$addr + 0x0c}] 0x03
 
 	# MCR - no flow control or loopback
-	mwb [expr $addr + 0x10] 0x00
+	mwb [expr {$addr + 0x10}] 0x00
 
 	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
-	mww [expr $addr + 0x30] 0xe001
+	mww [expr {$addr + 0x30}] 0xe001
 
 
 	########################