X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fcsb337.cfg;h=f75abbe0e8343b99ebd365f97c5f9e2f2b51e247;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=dd8bfa2de970ed8da7899bdf049ccbeaa65fd03b;hpb=8b7f813b234613646ffae0e27df74cb0b2eaf38d;p=fw%2Fopenocd

diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index dd8bfa2de..f75abbe0e 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -1,10 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Cogent CSB337
 #   http://cogcomp.com/csb_csb337.htm
 
 source [find target/at91rm9200.cfg]
 
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
-flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 # ETM9 trace port connector present on this board, 16 data pins.
 if { [info exists ETM_DRIVER] } {
@@ -18,7 +21,7 @@ if { [info exists ETM_DRIVER] } {
 
 proc csb337_clk_init { } {
 	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
-	jtag_khz 8
+	adapter speed 8
 
 	# CKGR_MOR:  start main oscillator (3.6864 MHz)
 	mww 0xfffffc20 0xff01
@@ -36,7 +39,7 @@ proc csb337_clk_init { } {
 	sleep 20
 
 	# CPU is in Normal Mode ... allows faster JTAG clock speed
-	jtag_khz 40000
+	adapter speed 40000
 }
 
 proc csb337_nor_init { } {
@@ -113,4 +116,4 @@ proc csb337_reset_init { } {
 
 $_TARGETNAME configure -event reset-init {csb337_reset_init}
 
-# vim:syntax tcl
+arm7_9 fast_memory_access enable