X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=e1cbb91204c796da63145cb0f7568aa68f384a5c;hb=fc74ccda52eced1f7be9fc99f071b0f47a7044ea;hp=9e0413a1963d4f22ca2827c1959dd2acbf1a3fcd;hpb=6d3cb807aaa60c4a4cd8ed49ae7860097bc1b3ce;p=fw%2Fopenocd

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 9e0413a19..e1cbb9120 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } {
 	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
 
 	mww 0xfffffc20 0x00004001
-	while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
 
 	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
 	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
 
 	mww 0xfffffc28 0x202a3f01
-	while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
 
 	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00000101
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Now change PMC_MCKR register to select PLLA.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00001302
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Processor and master clocks are now operating and stable at maximum frequency possible:
 	#	-> MCLK = 132.096 MHz
@@ -139,13 +139,13 @@ proc at91sam9g20_reset_init { } {
 	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
 	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
 	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
-	# a decent application note #6255B that covers this process. 
+	# a decent application note #6255B that covers this process.
 
 	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
 	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
 	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
-	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
-   
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
 	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
 	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
 
@@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } {
 
 	nand probe nandflash_cs3
 
-	# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
+	# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
 
 	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
 	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference