X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=a5831cd91cad1df5389d4791180e1f8791a24467;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=deb4da1540cae3b47d99440d79c755d0920ac5db;hpb=30da7c67cec8b315972377b5389735ff11f6042c;p=fw%2Fopenocd diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index deb4da154..a5831cd91 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ################################################################################################# # # # Author: Gary Carlson (gcarlson@carlson-minot.com) # @@ -9,13 +11,9 @@ # # source [find target/...cfg] -# Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of -# the AT91SAM9260 and shares the same tap ID as it. +source [find target/at91sam9g20.cfg] -set _CHIPNAME at91sam9g20 set _FLASHTYPE nandflash_cs3 -set _ENDIAN little -set _CPUTAPID 0x0792603f # Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore # the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is @@ -23,31 +21,9 @@ set _CPUTAPID 0x0792603f reset_config srst_only -# Set up the CPU and generate a new jtag tap for AT91SAM9G20. - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# Use caution changing the delays listed below. These seem to be -# affected by the board and type of JTAG adapter. A value of 200 ms seems -# to work reliably for the configuration listed in the file header above. - -adapter_nsrst_delay 200 +adapter srst delay 200 jtag_ntrst_delay 200 -# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). - -jtag_rclk 5 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. -# Both areas are 16 kB long. - -#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 -$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 - # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the # AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has # some powerful features, we want to have a special function that handles "reset init". To do this we declare @@ -66,9 +42,7 @@ at91sam9 rdy_busy 0 0xfffff800 13 at91sam9 ce 0 0xfffff800 14 proc read_register {register} { - set result "" - mem2array result 32 $register 1 - return $result(0) + return [read_memory $register 32 1] } proc at91sam9g20_reset_start { } { @@ -80,7 +54,7 @@ proc at91sam9g20_reset_start { } { # jtag speed without causing GDB keep alive problem. arm7_9 fast_memory_access disable - adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. + adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. halt ;# Make sure processor is halted, or error will result in following steps. wait_halt 10000 mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset. @@ -103,25 +77,25 @@ proc at91sam9g20_reset_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. mww 0xfffffc28 0x202a3f01 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00000101 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz @@ -129,7 +103,7 @@ proc at91sam9g20_reset_init { } { # Switch over to adaptive clocking. - adapter_khz 0 + adapter speed 0 # Enable faster DCC downloads and memory accesses. @@ -165,13 +139,13 @@ proc at91sam9g20_reset_init { } { # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3, # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers # is a little tedious to do here. If you have questions about how to do this, Atmel has - # a decent application note #6255B that covers this process. + # a decent application note #6255B that covers this process. mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle - mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, - + mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, + mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits) @@ -179,7 +153,7 @@ proc at91sam9g20_reset_init { } { nand probe nandflash_cs3 - # The AT91SAM9G20-EK evaluation board has build-in serial data flash also. + # The AT91SAM9G20-EK evaluation board has built-in serial data flash also. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference @@ -195,7 +169,7 @@ proc at91sam9g20_reset_init { } { # TRC = 9 cycles # TWR = 2 cycles # 9 column, 13 row, 4 banks - # refresh equal to or less then 7.8 us for commerical/industrial rated devices + # refresh equal to or less then 7.8 us for commercial/industrial rated devices # # Thus SDRAM_CR = 0xa6339279 @@ -242,4 +216,3 @@ proc at91sam9g20_reset_init { } { mww 0xffffea04 0x0000039c } -