X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=a5831cd91cad1df5389d4791180e1f8791a24467;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=03296c50e314287b868ed6c2515d82945d843bf7;hpb=5df5e89cf3caf02dc6f49a5d3c8aa8b1349a1dbf;p=fw%2Fopenocd

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 03296c50e..a5831cd91 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #################################################################################################
 #												#
 # Author: Gary Carlson (gcarlson@carlson-minot.com)						#
@@ -40,9 +42,7 @@ at91sam9 rdy_busy 0 0xfffff800 13
 at91sam9 ce 0 0xfffff800 14
 
 proc read_register {register} {
-        set result ""
-        mem2array result 32 $register 1
-        return $result(0)
+	return [read_memory $register 32 1]
 }
 
 proc at91sam9g20_reset_start { } {
@@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } {
 	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
 
 	mww 0xfffffc20 0x00004001
-	while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
 
 	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
 	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
 
 	mww 0xfffffc28 0x202a3f01
-	while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
 
 	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00000101
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Now change PMC_MCKR register to select PLLA.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 
 	mww 0xfffffc30 0x00001302
-	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
 	# Processor and master clocks are now operating and stable at maximum frequency possible:
 	#	-> MCLK = 132.096 MHz
@@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } {
 
 	nand probe nandflash_cs3
 
-	# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
+	# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
 
 	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
 	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference