X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9263-ek.cfg;fp=tcl%2Fboard%2Fat91sam9263-ek.cfg;h=b88efa9716f4005c9d673be4582ca14be08b45df;hb=f5657aa76e795e4ed5b13a9f5df943181a123e49;hp=645b1a7bd098b905883674491d738da7af3dc21f;hpb=82b6a41117fa99e760681d9f31163e7b68357e71;p=fw%2Fopenocd

diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg
index 645b1a7bd..b88efa971 100644
--- a/tcl/board/at91sam9263-ek.cfg
+++ b/tcl/board/at91sam9263-ek.cfg
@@ -25,10 +25,10 @@ proc at91sam9263ek_reset_init { } {
 	set config(master_pll_mul)	171
 
 	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
-	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
-	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
-	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
-	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]	;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]		;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
 
 	set config(wdt_mr_val) $val
 
@@ -37,22 +37,22 @@ proc at91sam9263ek_reset_init { } {
 	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
 
 	set val	[expr $::AT91_MATRIX_EBI0_DBPUC]
-	set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
-	set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
 	set config(matrix_ebicsa_val) $val
 
 	;# SDRAMC_CR - Configuration register
 	set val [expr $::AT91_SDRAMC_NC_9]
-	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
-	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
-	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
-	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
-	set val [expr ($val | (1 <<  8))]		;# Write Recovery Delay
-	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
-	set val [expr ($val | (2 << 16))]		;# Row Precharge Delay
-	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
-	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
-	set val [expr ($val | (1 << 28))]		;# Exit Self Refresh to Active Delay
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (1 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (2 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (1 << 28)}]		;# Exit Self Refresh to Active Delay
 
 	set config(sdram_cr_val) $val