X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9261-ek.cfg;h=c2d97b04e962f722f7b8aaa02ce7d5fc000e8226;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=3963e9373d81dea38edb753572645bbc5ce3a73e;hpb=22437fac283e9b931eabb7c0d1cb54d78e4bfed4;p=fw%2Fopenocd

diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
index 3963e9373..c2d97b04e 100644
--- a/tcl/board/at91sam9261-ek.cfg
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Atmel AT91SAM9261-EK eval board
 ################################################################################
@@ -29,30 +31,30 @@ proc at91sam9261ek_reset_init { } {
 	;# set master_pll_div	1
 	;# set master_pll_mul	13
 
-	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
-	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
-	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
-	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
-	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
 
 	set config(wdt_mr_val) $val
 
 	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
 	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
-	set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+	set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
 
 	;# SDRAMC_CR - Configuration register
-	set val [expr $::AT91_SDRAMC_NC_9]
-	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
-	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
-	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
-	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
-	set val [expr ($val | (2 <<  8))]		;# Write Recovery Delay
-	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
-	set val [expr ($val | (3 << 16))]		;# Row Precharge Delay
-	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
-	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
-	set val [expr ($val | (8 << 28))]		;# Exit Self Refresh to Active Delay
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (2 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (3 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (8 << 28)}]		;# Exit Self Refresh to Active Delay
 
 	set config(sdram_cr_val) $val