X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Ftarget%2Fimx27.cfg;h=240a8498f5943f9348bba436d9ff77dea9f36da4;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hp=c6fdf41c3476998b622ddf2e6d75441b8d86709a;hpb=91afc3dc3083a3d4f6a4104a5132d87c8ec03c7f;p=fw%2Fopenocd

diff --git a/src/target/target/imx27.cfg b/src/target/target/imx27.cfg
index c6fdf41c3..240a8498f 100644
--- a/src/target/target/imx27.cfg
+++ b/src/target/target/imx27.cfg
@@ -1,12 +1,42 @@
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
 
-# There are 2 taps on the chip:
-# The ETM
-jtag_device 4 0x1 0xf 0xe
-# The ARM926EJS
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME imx27
+}
 
-# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
-target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
 
+
+# Note above there are 2 taps 
+
+# The bs tap
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+   set _BSTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME bs  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size  0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable