X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fstm32_stlink.c;h=1c755084749e150cc597264c926981e4b49c570c;hb=7165e05cf64f5c24177239f9f9db577b45f1b52c;hp=64e83f534e6346d03b55befbef071fecc72e03d0;hpb=e2073cc18ae1380a7f6d0f61f49aab42de01b732;p=fw%2Fopenocd

diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c
index 64e83f534..1c7550847 100644
--- a/src/target/stm32_stlink.c
+++ b/src/target/stm32_stlink.c
@@ -38,6 +38,9 @@
 #include "cortex_m.h"
 #include "arm_semihosting.h"
 
+#define ARMV7M_SCS_DCRSR	0xe000edf4
+#define ARMV7M_SCS_DCRDR	0xe000edf8
+
 static inline struct stlink_interface_s *target_to_stlink(struct target *target)
 {
 	return target->tap->priv;
@@ -65,8 +68,38 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
 			LOG_ERROR("JTAG failure %i", retval);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",
-			  (int)num, *value);
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+		break;
+
+	case ARMV7M_FPSID:
+	case ARMV7M_FPEXC:
+		*value = 0;
+		break;
+
+	case ARMV7M_FPSCR:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+		break;
+
+	case ARMV7M_S0 ... ARMV7M_S31:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+		break;
+
+	case ARMV7M_D0 ... ARMV7M_D15:
+		value = 0;
 		break;
 
 	case ARMV7M_PRIMASK:
@@ -78,6 +111,8 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
 		 * it was removed from r1 docs, but still works.
 		 */
 		retval = stlink_if->layout->api->read_reg(stlink_if->fd, 20, value);
+		if (retval != ERROR_OK)
+			return retval;
 
 		switch (num) {
 		case ARMV7M_PRIMASK:
@@ -150,6 +185,35 @@ static int stm32_stlink_store_core_reg_u32(struct target *target,
 		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 		break;
 
+	case ARMV7M_FPSID:
+	case ARMV7M_FPEXC:
+		break;
+
+	case ARMV7M_FPSCR:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+		break;
+
+	case ARMV7M_S0 ... ARMV7M_S31:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+		break;
+
+	case ARMV7M_D0 ... ARMV7M_D15:
+		break;
+
 	case ARMV7M_PRIMASK:
 	case ARMV7M_BASEPRI:
 	case ARMV7M_FAULTMASK:
@@ -216,6 +280,7 @@ static int stm32_stlink_init_arch_info(struct target *target,
 	armv7m->store_core_reg_u32 = stm32_stlink_store_core_reg_u32;
 
 	armv7m->examine_debug_reason = stm32_stlink_examine_debug_reason;
+	armv7m->stlink = true;
 
 	return ERROR_OK;
 }
@@ -260,6 +325,7 @@ static int stm32_stlink_load_context(struct target *target)
 
 static int stlink_debug_entry(struct target *target)
 {
+	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct arm *arm = &armv7m->arm;
 	struct reg *r;
@@ -272,6 +338,9 @@ static int stlink_debug_entry(struct target *target)
 
 	stm32_stlink_load_context(target);
 
+	/* make sure we clear the vector catch bit */
+	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
+
 	r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
@@ -301,7 +370,7 @@ static int stlink_debug_entry(struct target *target)
 		armv7m->exception_number = 0;
 	}
 
-	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
+	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
 		armv7m_mode_strings[armv7m->core_mode],
 		*(uint32_t *)(arm->pc->value),
 		target_state_name(target));
@@ -336,7 +405,7 @@ static int stm32_stlink_poll(struct target *target)
 			return retval;
 
 		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-		LOG_DEBUG("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+		LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 	}
 
 	return ERROR_OK;
@@ -344,22 +413,54 @@ static int stm32_stlink_poll(struct target *target)
 
 static int stm32_stlink_assert_reset(struct target *target)
 {
-	int res;
+	int res = ERROR_OK;
 	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 	struct armv7m_common *armv7m = target_to_armv7m(target);
+	bool use_srst_fallback = true;
 
 	LOG_DEBUG("%s", __func__);
 
+	enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+	bool srst_asserted = false;
+
+	if (jtag_reset_config & RESET_SRST_NO_GATING) {
+		jtag_add_reset(0, 1);
+		res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+		srst_asserted = true;
+	}
+
+	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
+
+	/* only set vector catch if halt is requested */
+	if (target->reset_halt)
+		stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+	else
+		stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
+
+	if (jtag_reset_config & RESET_HAS_SRST) {
+		if (!srst_asserted) {
+			jtag_add_reset(0, 1);
+			res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+		}
+		if (res == ERROR_COMMAND_NOTFOUND)
+			LOG_ERROR("Hardware srst not supported, falling back to software reset");
+		else if (res == ERROR_OK) {
+			/* hardware srst supported */
+			use_srst_fallback = false;
+		}
+	}
+
+	if (use_srst_fallback) {
+		/* stlink v1 api does not support hardware srst, so we use a software reset fallback */
+		stlink_if->layout->api->write_debug_reg(stlink_if->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+	}
+
 	res = stlink_if->layout->api->reset(stlink_if->fd);
 
 	if (res != ERROR_OK)
 		return res;
 
-	/* virtual assert reset, we need it for the internal
-	 * jtag state machine
-	 */
-	jtag_add_reset(1, 1);
-
 	/* registers are now invalid */
 	register_cache_invalidate(armv7m->core_cache);
 
@@ -376,9 +477,15 @@ static int stm32_stlink_assert_reset(struct target *target)
 static int stm32_stlink_deassert_reset(struct target *target)
 {
 	int res;
+	struct stlink_interface_s *stlink_if = target_to_stlink(target);
+
+	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
 	LOG_DEBUG("%s", __func__);
 
+	if (jtag_reset_config & RESET_HAS_SRST)
+		stlink_if->layout->api->assert_srst(stlink_if->fd, 1);
+
 	/* virtual deassert reset, we need it for the internal
 	 * jtag state machine
 	 */
@@ -436,7 +543,7 @@ static int stm32_stlink_resume(struct target *target, int current,
 	struct breakpoint *breakpoint = NULL;
 	struct reg *pc;
 
-	LOG_DEBUG("%s %d %x %d %d", __func__, current, address,
+	LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address,
 			handle_breakpoints, debug_execution);
 
 	if (target->state != TARGET_HALTED) {
@@ -488,6 +595,7 @@ static int stm32_stlink_resume(struct target *target, int current,
 		return res;
 
 	target->state = TARGET_RUNNING;
+	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
@@ -548,7 +656,7 @@ static int stm32_stlink_step(struct target *target, int current,
 	stlink_debug_entry(target);
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
-	LOG_INFO("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
+	LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 
 	return ERROR_OK;
 }
@@ -560,14 +668,13 @@ static int stm32_stlink_read_memory(struct target *target, uint32_t address,
 	int res;
 	uint32_t buffer_threshold = 128;
 	uint32_t addr_increment = 4;
-	uint8_t *dst = buffer;
 	uint32_t c;
 	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
+	LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
 
 	/* prepare byte count, buffer threshold
 	 * and address increment for none 32bit access
@@ -586,16 +693,16 @@ static int stm32_stlink_read_memory(struct target *target, uint32_t address,
 
 		if (size != 4)
 			res = stlink_if->layout->api->read_mem8(stlink_if->fd,
-					address, c, dst);
+					address, c, buffer);
 		else
 			res = stlink_if->layout->api->read_mem32(stlink_if->fd,
-					address, c, (uint32_t *)dst);
+					address, c, buffer);
 
 		if (res != ERROR_OK)
 			return res;
 
 		address += (c * addr_increment);
-		dst += (c * addr_increment);
+		buffer += (c * addr_increment);
 		count -= c;
 	}
 
@@ -609,14 +716,13 @@ static int stm32_stlink_write_memory(struct target *target, uint32_t address,
 	int res;
 	uint32_t buffer_threshold = 128;
 	uint32_t addr_increment = 4;
-	const uint8_t *dst = buffer;
 	uint32_t c;
 	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
+	LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
 
 	/* prepare byte count, buffer threshold
 	 * and address increment for none 32bit access
@@ -635,16 +741,16 @@ static int stm32_stlink_write_memory(struct target *target, uint32_t address,
 
 		if (size != 4)
 			res = stlink_if->layout->api->write_mem8(stlink_if->fd,
-					address, c, dst);
+					address, c, buffer);
 		else
 			res = stlink_if->layout->api->write_mem32(stlink_if->fd,
-					address, c, (uint32_t *)dst);
+					address, c, buffer);
 
 		if (res != ERROR_OK)
 			return res;
 
 		address += (c * addr_increment);
-		dst += (c * addr_increment);
+		buffer += (c * addr_increment);
 		count -= c;
 	}
 
@@ -658,12 +764,20 @@ static int stm32_stlink_bulk_write_memory(struct target *target,
 	return stm32_stlink_write_memory(target, address, 4, count, buffer);
 }
 
+static const struct command_registration stm32_stlink_command_handlers[] = {
+	{
+		.chain = arm_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 struct target_type stm32_stlink_target = {
 	.name = "stm32_stlink",
 
 	.init_target = stm32_stlink_init_target,
 	.target_create = stm32_stlink_target_create,
 	.examine = cortex_m3_examine,
+	.commands = stm32_stlink_command_handlers,
 
 	.poll = stm32_stlink_poll,
 	.arch_state = armv7m_arch_state,