X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fstm32_stlink.c;h=1c755084749e150cc597264c926981e4b49c570c;hb=7165e05cf64f5c24177239f9f9db577b45f1b52c;hp=4044654cfe37c49b2d940d831889dd4234cde4b9;hpb=d469c686d9c4aaef7dc0ff8376142b8fdd6d1dbd;p=fw%2Fopenocd

diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c
index 4044654cf..1c7550847 100644
--- a/src/target/stm32_stlink.c
+++ b/src/target/stm32_stlink.c
@@ -111,6 +111,8 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
 		 * it was removed from r1 docs, but still works.
 		 */
 		retval = stlink_if->layout->api->read_reg(stlink_if->fd, 20, value);
+		if (retval != ERROR_OK)
+			return retval;
 
 		switch (num) {
 		case ARMV7M_PRIMASK:
@@ -278,6 +280,7 @@ static int stm32_stlink_init_arch_info(struct target *target,
 	armv7m->store_core_reg_u32 = stm32_stlink_store_core_reg_u32;
 
 	armv7m->examine_debug_reason = stm32_stlink_examine_debug_reason;
+	armv7m->stlink = true;
 
 	return ERROR_OK;
 }
@@ -322,6 +325,7 @@ static int stm32_stlink_load_context(struct target *target)
 
 static int stlink_debug_entry(struct target *target)
 {
+	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct arm *arm = &armv7m->arm;
 	struct reg *r;
@@ -334,6 +338,9 @@ static int stlink_debug_entry(struct target *target)
 
 	stm32_stlink_load_context(target);
 
+	/* make sure we clear the vector catch bit */
+	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
+
 	r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
@@ -424,7 +431,12 @@ static int stm32_stlink_assert_reset(struct target *target)
 	}
 
 	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
-	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+
+	/* only set vector catch if halt is requested */
+	if (target->reset_halt)
+		stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+	else
+		stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
 
 	if (jtag_reset_config & RESET_HAS_SRST) {
 		if (!srst_asserted) {
@@ -440,7 +452,7 @@ static int stm32_stlink_assert_reset(struct target *target)
 	}
 
 	if (use_srst_fallback) {
-		/* stlink v1 api does support hardware srst, so we use a software reset fallback */
+		/* stlink v1 api does not support hardware srst, so we use a software reset fallback */
 		stlink_if->layout->api->write_debug_reg(stlink_if->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 	}
 
@@ -583,6 +595,7 @@ static int stm32_stlink_resume(struct target *target, int current,
 		return res;
 
 	target->state = TARGET_RUNNING;
+	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
@@ -751,12 +764,20 @@ static int stm32_stlink_bulk_write_memory(struct target *target,
 	return stm32_stlink_write_memory(target, address, 4, count, buffer);
 }
 
+static const struct command_registration stm32_stlink_command_handlers[] = {
+	{
+		.chain = arm_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 struct target_type stm32_stlink_target = {
 	.name = "stm32_stlink",
 
 	.init_target = stm32_stlink_init_target,
 	.target_create = stm32_stlink_target_create,
 	.examine = cortex_m3_examine,
+	.commands = stm32_stlink_command_handlers,
 
 	.poll = stm32_stlink_poll,
 	.arch_state = armv7m_arch_state,