X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fnds32_v3_common.c;h=f2efab441744711fc8e516bf98dc05905e5955ae;hb=382148e4dd437978997d668f6ec715ddcec1c46e;hp=b524679e286e2eae1c4fdc8e90e21cff86360fb6;hpb=54d8a801b2210a31ce48a77ff51933f4f23a84e9;p=fw%2Fopenocd diff --git a/src/target/nds32_v3_common.c b/src/target/nds32_v3_common.c index b524679e2..f2efab441 100644 --- a/src/target/nds32_v3_common.c +++ b/src/target/nds32_v3_common.c @@ -1,21 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2013 Andes Technology * * Hsiangkai Wang * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -29,18 +16,6 @@ #include "nds32_aice.h" #include "nds32_v3_common.h" -static struct breakpoint syscall_breakpoint = { - 0x80, - 0, - 4, - BKPT_SOFT, - 0, - NULL, - NULL, - 0x515CA11, - 0, -}; - static struct nds32_v3_common_callback *v3_common_callback; static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no) @@ -90,23 +65,24 @@ static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint) if (enable_watchpoint) CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target)); + struct breakpoint *syscall_break = &(nds32->syscall_break); if (nds32->virtual_hosting) { - if (syscall_breakpoint.set) { + if (syscall_break->is_set) { /** disable virtual hosting */ /* remove breakpoint at syscall entry */ - target_remove_breakpoint(nds32->target, &syscall_breakpoint); - syscall_breakpoint.set = 0; + target_remove_breakpoint(nds32->target, syscall_break); + syscall_break->is_set = false; uint32_t value_pc; nds32_get_mapped_reg(nds32, PC, &value_pc); - if (value_pc == syscall_breakpoint.address) + if (value_pc == syscall_break->address) /** process syscall for virtual hosting */ nds32->hit_syscall = true; } } - if (ERROR_OK != nds32_examine_debug_reason(nds32)) { + if (nds32_examine_debug_reason(nds32) != ERROR_OK) { nds32->target->state = backup_state; /* re-activate all hardware breakpoints & watchpoints */ @@ -218,10 +194,12 @@ static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoin } /* insert breakpoint at syscall entry */ - syscall_breakpoint.address = syscall_address; - syscall_breakpoint.type = BKPT_SOFT; - syscall_breakpoint.set = 1; - target_add_breakpoint(target, &syscall_breakpoint); + struct breakpoint *syscall_break = &(nds32->syscall_break); + + syscall_break->address = syscall_address; + syscall_break->type = BKPT_SOFT; + syscall_break->is_set = true; + target_add_breakpoint(target, syscall_break); } return ERROR_OK; @@ -240,6 +218,7 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, uint32_t match_count; int32_t i; static int32_t number_of_hard_break; + uint32_t bp_control; if (number_of_hard_break == 0) { aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); @@ -255,6 +234,14 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, if (match_bits & (1 << i)) { aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address); match_count++; + + /* If target hits multiple read/access watchpoint, + * select the first one. */ + aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &bp_control); + if (0x3 == (bp_control & 0x3)) { + match_count = 1; + break; + } } } @@ -270,8 +257,8 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, nds32_get_mapped_reg(nds32, PC, &val_pc); - if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) || - (NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) { + if ((reason == NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE) || + (reason == NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE)) { if (edmsw & 0x4) /* check EDMSW.IS_16BIT */ val_pc -= 2; else @@ -281,8 +268,8 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, nds32_read_opcode(nds32, val_pc, &opcode); nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction); - LOG_DEBUG("PC: 0x%08x, access start: 0x%08x, end: 0x%08x", val_pc, - instruction.access_start, instruction.access_end); + LOG_DEBUG("PC: 0x%08" PRIx32 ", access start: 0x%08" PRIx32 ", end: 0x%08" PRIx32, + val_pc, instruction.access_start, instruction.access_end); /* check if multiple hits in the access range */ uint32_t in_range_watch_count = 0; @@ -322,7 +309,7 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, return ERROR_FAIL; } else if (match_count == 0) { /* global stop is precise exception */ - if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) { + if ((reason == NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP) && nds32->global_stop) { /* parse instruction to get correct access address */ uint32_t val_pc; uint32_t opcode; @@ -369,14 +356,8 @@ int nds32_v3_target_request_data(struct target *target, return ERROR_OK; } -int nds32_v3_soft_reset_halt(struct target *target) -{ - struct aice_port_s *aice = target_to_aice(target); - return aice_assert_srst(aice, AICE_RESET_HOLD); -} - int nds32_v3_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *checksum) + target_addr_t address, uint32_t count, uint32_t *checksum) { LOG_WARNING("Not implemented: %s", __func__); @@ -442,8 +423,8 @@ int nds32_v3_run_algorithm(struct target *target, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, - uint32_t exit_point, + target_addr_t entry_point, + target_addr_t exit_point, int timeout_ms, void *arch_info) { @@ -452,19 +433,19 @@ int nds32_v3_run_algorithm(struct target *target, return ERROR_FAIL; } -int nds32_v3_read_buffer(struct target *target, uint32_t address, +int nds32_v3_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer) { struct nds32 *nds32 = target_to_nds32(target); struct nds32_memory *memory = &(nds32->memory); - if ((NDS_MEMORY_ACC_CPU == memory->access_channel) && + if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && (target->state != TARGET_HALTED)) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - uint32_t physical_address; + target_addr_t physical_address; /* BUG: If access range crosses multiple pages, the translation will not correct * for second page or so. */ @@ -482,7 +463,7 @@ int nds32_v3_read_buffer(struct target *target, uint32_t address, * Because hardware will turn off IT/DT by default, it MUST translate virtual address * to physical address. */ - if (ERROR_OK == target->type->virt2phys(target, address, &physical_address)) + if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) address = physical_address; else return ERROR_FAIL; @@ -510,19 +491,19 @@ int nds32_v3_read_buffer(struct target *target, uint32_t address, return result; } -int nds32_v3_write_buffer(struct target *target, uint32_t address, +int nds32_v3_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer) { struct nds32 *nds32 = target_to_nds32(target); struct nds32_memory *memory = &(nds32->memory); - if ((NDS_MEMORY_ACC_CPU == memory->access_channel) && + if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && (target->state != TARGET_HALTED)) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - uint32_t physical_address; + target_addr_t physical_address; /* BUG: If access range crosses multiple pages, the translation will not correct * for second page or so. */ @@ -540,25 +521,31 @@ int nds32_v3_write_buffer(struct target *target, uint32_t address, * Because hardware will turn off IT/DT by default, it MUST translate virtual address * to physical address. */ - if (ERROR_OK == target->type->virt2phys(target, address, &physical_address)) + if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) address = physical_address; else return ERROR_FAIL; if (nds32->hit_syscall) { - /* Use bus mode to access memory during virtual hosting */ struct aice_port_s *aice = target_to_aice(target); enum nds_memory_access origin_access_channel; - int result; - origin_access_channel = memory->access_channel; - memory->access_channel = NDS_MEMORY_ACC_BUS; - aice_memory_access(aice, NDS_MEMORY_ACC_BUS); + /* If target has no cache, use BUS mode to access memory. */ + if ((memory->dcache.line_size == 0) + || (memory->dcache.enable == false)) { + /* There is no Dcache or Dcache is disabled. */ + memory->access_channel = NDS_MEMORY_ACC_BUS; + aice_memory_access(aice, NDS_MEMORY_ACC_BUS); + } + + int result; result = nds32_gdb_fileio_write_memory(nds32, address, size, buffer); - memory->access_channel = origin_access_channel; - aice_memory_access(aice, origin_access_channel); + if (origin_access_channel == NDS_MEMORY_ACC_CPU) { + memory->access_channel = NDS_MEMORY_ACC_CPU; + aice_memory_access(aice, NDS_MEMORY_ACC_CPU); + } return result; } @@ -566,19 +553,19 @@ int nds32_v3_write_buffer(struct target *target, uint32_t address, return nds32_write_buffer(target, address, size, buffer); } -int nds32_v3_read_memory(struct target *target, uint32_t address, +int nds32_v3_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct nds32 *nds32 = target_to_nds32(target); struct nds32_memory *memory = &(nds32->memory); - if ((NDS_MEMORY_ACC_CPU == memory->access_channel) && + if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && (target->state != TARGET_HALTED)) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - uint32_t physical_address; + target_addr_t physical_address; /* BUG: If access range crosses multiple pages, the translation will not correct * for second page or so. */ @@ -596,7 +583,7 @@ int nds32_v3_read_memory(struct target *target, uint32_t address, * Because hardware will turn off IT/DT by default, it MUST translate virtual address * to physical address. */ - if (ERROR_OK == target->type->virt2phys(target, address, &physical_address)) + if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) address = physical_address; else return ERROR_FAIL; @@ -624,19 +611,19 @@ int nds32_v3_read_memory(struct target *target, uint32_t address, return result; } -int nds32_v3_write_memory(struct target *target, uint32_t address, +int nds32_v3_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct nds32 *nds32 = target_to_nds32(target); struct nds32_memory *memory = &(nds32->memory); - if ((NDS_MEMORY_ACC_CPU == memory->access_channel) && + if ((memory->access_channel == NDS_MEMORY_ACC_CPU) && (target->state != TARGET_HALTED)) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - uint32_t physical_address; + target_addr_t physical_address; /* BUG: If access range crosses multiple pages, the translation will not correct * for second page or so. */ @@ -654,7 +641,7 @@ int nds32_v3_write_memory(struct target *target, uint32_t address, * Because hardware will turn off IT/DT by default, it MUST translate virtual address * to physical address. */ - if (ERROR_OK == target->type->virt2phys(target, address, &physical_address)) + if (target->type->virt2phys(target, address, &physical_address) == ERROR_OK) address = physical_address; else return ERROR_FAIL;