X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.h;h=a6ed95a509b5bdc9c287ecbe4ed98ade5ccec42d;hb=719f9ecde32ab60bcb65913454a9340c5754cee4;hp=b25bd0265299a4b0465fc0d36cf64d113376ca00;hpb=53590217eee6106782b2bb85ed334adf7c5e68c1;p=fw%2Fopenocd

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index b25bd0265..a6ed95a50 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -23,9 +23,9 @@
 #ifndef MIPS_EJTAG
 #define MIPS_EJTAG
 
-#include "types.h"
-#include "jtag.h"
+#include <jtag/jtag.h>
 
+/* tap instructions */
 #define EJTAG_INST_IDCODE		0x01
 #define EJTAG_INST_IMPCODE		0x03
 #define EJTAG_INST_ADDRESS		0x08
@@ -38,8 +38,20 @@
 #define EJTAG_INST_TCBCONTROLA	0x10
 #define EJTAG_INST_TCBCONTROLB	0x11
 #define EJTAG_INST_TCBDATA		0x12
-#define EJTAG_INST_BYPASS		0x1F
+#define EJTAG_INST_BYPASS		0xFF
 
+/* microchip PIC32MX specific instructions */
+#define MTAP_SW_MTAP			0x04
+#define MTAP_SW_ETAP			0x05
+#define MTAP_COMMAND			0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST			0xd1
+#define MCHP_DE_ASSERT_RST		0xd0
+#define MCHP_ERASE				0xfc
+#define MCHP_STATUS				0x00
+
+/* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
 #define EJTAG_CTRL_TIF			(1 << 2)
 #define EJTAG_CTRL_BRKST		(1 << 3)
@@ -85,23 +97,53 @@
 #define EJTAG_DEBUG_DM			(1 << 30)
 #define EJTAG_DEBUG_DBD			(1 << 31)
 
-typedef struct mips_ejtag_s
+/* implementaion register bits */
+#define EJTAG_IMP_R3K			(1 << 28)
+#define EJTAG_IMP_DINT			(1 << 24)
+#define EJTAG_IMP_NODMA			(1 << 14)
+#define EJTAG_IMP_MIPS16		(1 << 16)
+#define EJTAG_DCR_MIPS64		(1 << 0)
+
+/* Debug Control Register DCR */
+#define EJTAG_DCR				0xFF300000
+#define EJTAG_DCR_ENM			(1 << 29)
+#define EJTAG_DCR_DB			(1 << 17)
+#define EJTAG_DCR_IB			(1 << 16)
+#define EJTAG_DCR_INTE			(1 << 4)
+
+/* breakpoint support */
+#define EJTAG_IBS				0xFF301000
+#define EJTAG_IBA1				0xFF301100
+#define EJTAG_DBS				0xFF302000
+#define EJTAG_DBA1				0xFF302100
+#define	EJTAG_DBCn_NOSB			(1 << 13)
+#define	EJTAG_DBCn_NOLB			(1 << 12)
+#define	EJTAG_DBCn_BLM_MASK		0xff
+#define	EJTAG_DBCn_BLM_SHIFT	4
+#define	EJTAG_DBCn_BE			(1 << 0)
+
+struct mips_ejtag
 {
-	int chain_pos;
-	u32 impcode;
-//	int use_dma;
-	u32 ejtag_ctrl;
-} mips_ejtag_t;
+	struct jtag_tap *tap;
+	uint32_t impcode;
+	uint32_t idcode;
+	uint32_t ejtag_ctrl;
+	int fast_access_save;
+};
 
-extern int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler);
-extern int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info);
-extern int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts);
-extern int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t handler);
-extern int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t handler);
-extern int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data);
+void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
+		int new_instr);
+int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
+int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
+int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
+void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
+int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
 
-extern int mips_ejtag_init(mips_ejtag_t *ejtag_info);
-extern int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step);
-extern int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg);
+int mips_ejtag_init(struct mips_ejtag *ejtag_info);
+int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
+int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg);
 
 #endif /* MIPS_EJTAG */