X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=1ac682b88ac644d327c1c7c21c954db0ac3c2f5f;hb=47f2305229486f14eed948025c21c6ab73471d4e;hp=6f73d321de85f35c64b361806609a71e773578ab;hpb=eb51d4f68b96dba5f955c683e92d2805f0828f81;p=fw%2Fopenocd

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 6f73d321d..1ac682b88 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -24,54 +24,53 @@
 #define MIPS32_H
 
 #include "target.h"
-#include "register.h"
-#include "mips_ejtag.h"
 #include "mips32_pracc.h"
 
+
 #define MIPS32_COMMON_MAGIC		0xB320B320
 
 /* offsets into mips32 core register cache */
-enum 
+enum
 {
 	MIPS32_PC = 37,
 	MIPS32NUMCOREREGS
 };
 
-typedef struct mips32_comparator_s
+struct mips32_comparator
 {
 	int used;
 	//int type;
-	u32 bp_value;
-	u32 reg_address;
-} mips32_comparator_t;
+	uint32_t bp_value;
+	uint32_t reg_address;
+};
 
-typedef struct mips32_common_s
+struct mips32_common
 {
-	u32 common_magic;
+	uint32_t common_magic;
 	void *arch_info;
-	reg_cache_t *core_cache;
-	mips_ejtag_t ejtag_info;
-	u32 core_regs[MIPS32NUMCOREREGS];
-	
+	struct reg_cache *core_cache;
+	struct mips_ejtag ejtag_info;
+	uint32_t core_regs[MIPS32NUMCOREREGS];
+
 	int bp_scanned;
 	int num_inst_bpoints;
 	int num_data_bpoints;
 	int num_inst_bpoints_avail;
 	int num_data_bpoints_avail;
-	mips32_comparator_t *inst_break_list;
-	mips32_comparator_t *data_break_list;
-	
+	struct mips32_comparator *inst_break_list;
+	struct mips32_comparator *data_break_list;
+
 	/* register cache to processor synchronization */
-	int (*read_core_reg)(struct target_s *target, int num);
-	int (*write_core_reg)(struct target_s *target, int num);
-} mips32_common_t;
+	int (*read_core_reg)(struct target *target, int num);
+	int (*write_core_reg)(struct target *target, int num);
+};
 
-typedef struct mips32_core_reg_s
+struct mips32_core_reg
 {
-	u32 num;
-	target_t *target;
-	mips32_common_t *mips32_common;
-} mips32_core_reg_t;
+	uint32_t num;
+	struct target *target;
+	struct mips32_common *mips32_common;
+};
 
 #define MIPS32_OP_BEQ	0x04
 #define MIPS32_OP_BNE	0x05
@@ -94,9 +93,9 @@ typedef struct mips32_core_reg_s
 #define MIPS32_COP0_MF	0x00
 #define MIPS32_COP0_MT	0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<5) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr)	(((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
+#define MIPS32_J_INST(opcode, addr)	(((opcode) << 26) |(addr))
 
 #define MIPS32_NOP					0
 #define MIPS32_ADDI(tar, src, val)	MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
@@ -124,17 +123,32 @@ typedef struct mips32_core_reg_s
 #define MIPS32_SDBBP				0x7000003F
 #define MIPS16_SDBBP 				0xE801
 
-extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
-extern int mips32_restore_context(target_t *target);
-extern int mips32_save_context(target_t *target);
-extern reg_cache_t *mips32_build_reg_cache(target_t *target);
-extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
-extern int mips32_configure_break_unit(struct target_s *target);
-extern int mips32_examine(struct target_s *target);
-
-extern int mips32_register_commands(struct command_context_s *cmd_ctx);
-extern int mips32_invalidate_core_regs(target_t *target);
-extern int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
+int mips32_arch_state(struct target *target);
+
+int mips32_init_arch_info(struct target *target,
+		struct mips32_common *mips32, struct jtag_tap *tap);
+
+int mips32_restore_context(struct target *target);
+int mips32_save_context(struct target *target);
+
+struct reg_cache *mips32_build_reg_cache(struct target *target);
+
+int mips32_run_algorithm(struct target *target,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
+		uint32_t entry_point, uint32_t exit_point,
+		int timeout_ms, void *arch_info);
+
+int mips32_configure_break_unit(struct target *target);
+
+int mips32_enable_interrupts(struct target *target, int enable);
+
+int mips32_examine(struct target *target);
+
+int mips32_register_commands(struct command_context *cmd_ctx);
+
+int mips32_invalidate_core_regs(struct target *target);
+int mips32_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size);
 
 #endif	/*MIPS32_H*/