X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=5d9f343fb0acbf22397d900254ac5bfc978c255c;hb=3c2eabd20f5182c53f0bfb0c6f2a9f2595434e87;hp=bcf96147f13f149d15599ea9aae6505b51aff9ed;hpb=27ad4524afc3262e64aff2ae917d10881e8d6823;p=fw%2Fopenocd diff --git a/src/target/mips32.c b/src/target/mips32.c index bcf96147f..5d9f343fb 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -27,11 +27,7 @@ #endif #include "mips32.h" -#include "jtag.h" -#include "log.h" -#include -#include char* mips32_core_reg_list[] = { @@ -85,18 +81,16 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = {37, NULL, NULL}, }; -u8 mips32_gdb_dummy_fsr_value[] = {0, 0, 0, 0}; +/* number of mips dummy fp regs fp0 - fp31 + fsr and fir + * we also add 18 unknown registers to handle gdb requests */ -reg_t mips32_gdb_dummy_fsr_reg = -{ - "GDB dummy floating-point status register", mips32_gdb_dummy_fsr_value, 0, 1, 32, NULL, 0, NULL, 0 -}; +#define MIPS32NUMFPREGS 34 + 18 -u8 mips32_gdb_dummy_fir_value[] = {0, 0, 0, 0}; +uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -reg_t mips32_gdb_dummy_fir_reg = +reg_t mips32_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", mips32_gdb_dummy_fir_value, 0, 1, 32, NULL, 0, NULL, 0 + "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0 }; int mips32_core_reg_arch_type = -1; @@ -118,11 +112,11 @@ int mips32_get_core_reg(reg_t *reg) return retval; } -int mips32_set_core_reg(reg_t *reg, u8 *buf) +int mips32_set_core_reg(reg_t *reg, uint8_t *buf) { mips32_core_reg_t *mips32_reg = reg->arch_info; target_t *target = mips32_reg->target; - u32 value = buf_get_u32(buf, 0, 32); + uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { @@ -138,7 +132,7 @@ int mips32_set_core_reg(reg_t *reg, u8 *buf) int mips32_read_core_reg(struct target_s *target, int num) { - u32 reg_value; + uint32_t reg_value; mips32_core_reg_t *mips_core_reg; /* get pointers to arch-specific information */ @@ -158,7 +152,7 @@ int mips32_read_core_reg(struct target_s *target, int num) int mips32_write_core_reg(struct target_s *target, int num) { - u32 reg_value; + uint32_t reg_value; mips32_core_reg_t *mips_core_reg; /* get pointers to arch-specific information */ @@ -198,8 +192,8 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ mips32_common_t *mips32 = target->arch_info; int i; - /* include fsr/fir reg */ - *reg_list_size = MIPS32NUMCOREREGS + 2; + /* include floating point registers */ + *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); for (i = 0; i < MIPS32NUMCOREREGS; i++) @@ -208,9 +202,11 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ } /* add dummy floating points regs */ - (*reg_list)[38] = &mips32_gdb_dummy_fsr_reg; - (*reg_list)[39] = &mips32_gdb_dummy_fir_reg; - + for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++) + { + (*reg_list)[i] = &mips32_gdb_dummy_fp_reg; + } + return ERROR_OK; } @@ -290,8 +286,7 @@ reg_cache_t *mips32_build_reg_cache(target_t *target) if (mips32_core_reg_arch_type == -1) mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg); - register_init_dummy(&mips32_gdb_dummy_fsr_reg); - register_init_dummy(&mips32_gdb_dummy_fir_reg); + register_init_dummy(&mips32_gdb_dummy_fp_reg); /* Build the process context cache */ cache->name = "mips32 registers"; @@ -320,7 +315,7 @@ reg_cache_t *mips32_build_reg_cache(target_t *target) return cache; } -int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant) +int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap) { target->arch_info = mips32; mips32->common_magic = MIPS32_COMMON_MAGIC; @@ -329,7 +324,7 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_p mips32->bp_scanned = 0; mips32->data_break_list = NULL; - mips32->ejtag_info.chain_pos = chain_pos; + mips32->ejtag_info.tap = tap; mips32->read_core_reg = mips32_read_core_reg; mips32->write_core_reg = mips32_write_core_reg; @@ -341,7 +336,7 @@ int mips32_register_commands(struct command_context_s *cmd_ctx) return ERROR_OK; } -int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info) +int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) { /*TODO*/ return ERROR_OK; @@ -351,9 +346,9 @@ int mips32_examine(struct target_s *target) { mips32_common_t *mips32 = target->arch_info; - if (!target->type->examined) + if (!target_was_examined(target)) { - target->type->examined = 1; + target_set_examined(target); /* we will configure later */ mips32->bp_scanned = 0; @@ -371,7 +366,7 @@ int mips32_configure_break_unit(struct target_s *target) /* get pointers to arch-specific information */ mips32_common_t *mips32 = target->arch_info; int retval; - u32 dcr, bpinfo; + uint32_t dcr, bpinfo; int i; if (mips32->bp_scanned) @@ -425,3 +420,41 @@ int mips32_configure_break_unit(struct target_s *target) return ERROR_OK; } + +int mips32_enable_interrupts(struct target_s *target, int enable) +{ + int retval; + int update = 0; + uint32_t dcr; + + /* read debug control register */ + if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) + return retval; + + if (enable) + { + if (!(dcr & (1<<4))) + { + /* enable interrupts */ + dcr |= (1<<4); + update = 1; + } + } + else + { + if (dcr & (1<<4)) + { + /* disable interrupts */ + dcr &= ~(1<<4); + update = 1; + } + } + + if (update) + { + if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK) + return retval; + } + + return ERROR_OK; +}