X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Flakemont.c;h=64da29c641ef526d8bc03300eb317aa4cb4ee245;hb=3adbec9aab95808222071eb09014f28fbb6ad1be;hp=055d94340114e44e727ed5c7ca213d3b0b98c4c7;hpb=ec1fde57979ab9331fc939633b0461ef4af7def7;p=fw%2Fopenocd diff --git a/src/target/lakemont.c b/src/target/lakemont.c index 055d94340..64da29c64 100644 --- a/src/target/lakemont.c +++ b/src/target/lakemont.c @@ -1,25 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* - * Copyright(c) 2013 Intel Corporation. + * Copyright(c) 2013-2016 Intel Corporation. * * Adrian Burns (adrian.burns@intel.com) * Thomas Faust (thomas.faust@intel.com) * Ivan De Cesaris (ivan.de.cesaris@intel.com) * Julien Carreno (julien.carreno@intel.com) * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * Jessica Gomez (jessica.gomez.hernandez@intel.com) * * Contact Information: * Intel Corporation @@ -227,7 +216,7 @@ static int irscan(struct target *t, uint8_t *out, { int retval = ERROR_OK; struct x86_32_common *x86_32 = target_to_x86_32(t); - if (NULL == t->tap) { + if (!t->tap) { retval = ERROR_FAIL; LOG_ERROR("%s invalid target tap", __func__); return retval; @@ -260,7 +249,7 @@ static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len) int retval = ERROR_OK; uint64_t data = 0; struct x86_32_common *x86_32 = target_to_x86_32(t); - if (NULL == t->tap) { + if (!t->tap) { retval = ERROR_FAIL; LOG_ERROR("%s invalid target tap", __func__); return retval; @@ -283,7 +272,7 @@ static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len) return retval; } } - if (in != NULL) { + if (in) { if (len >= 8) { for (int n = (len / 8) - 1 ; n >= 0; n--) data = (data << 8) + *(in+n); @@ -322,15 +311,15 @@ static int restore_context(struct target *t) } for (i = 0; i < (x86_32->cache->num_regs); i++) { - x86_32->cache->reg_list[i].dirty = 0; - x86_32->cache->reg_list[i].valid = 0; + x86_32->cache->reg_list[i].dirty = false; + x86_32->cache->reg_list[i].valid = false; } return err; } /* * we keep reg_cache in sync with hardware at halt/resume time, we avoid - * writing to real hardware here bacause pm_regs reflects the hardware + * writing to real hardware here because pm_regs reflects the hardware * while we are halted then reg_cache syncs with hw on resume * TODO - in order for "reg eip force" to work it assume get/set reads * and writes from hardware, may be other reasons also because generally @@ -357,13 +346,13 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf) if (check_not_halted(t)) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } static const struct reg_arch_type lakemont_reg_type = { - /* these get called if reg_cache doesnt have a "valid" value + /* these get called if reg_cache doesn't have a "valid" value * of an individual reg eg "reg eip" but not for "reg" block */ .get = lakemont_get_core_reg, @@ -381,7 +370,7 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t) struct reg_feature *feature; int i; - if (cache == NULL || reg_list == NULL || arch_info == NULL) { + if (!cache || !reg_list || !arch_info) { free(cache); free(reg_list); free(arch_info); @@ -405,8 +394,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t) reg_list[i].name = regs[i].name; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &lakemont_reg_type; reg_list[i].arch_info = &arch_info[i]; @@ -444,6 +433,8 @@ static uint32_t get_tapstatus(struct target *t) static int enter_probemode(struct target *t) { uint32_t tapstatus = 0; + int retries = 100; + tapstatus = get_tapstatus(t); LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus); if (tapstatus & TS_PM_BIT) { @@ -456,15 +447,17 @@ static int enter_probemode(struct target *t) scan.out[0] = 1; if (drscan(t, scan.out, scan.in, 1) != ERROR_OK) return ERROR_FAIL; - tapstatus = get_tapstatus(t); - LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus); - if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT))) - return ERROR_OK; - else { - LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32 - , __func__, tapstatus); - return ERROR_FAIL; + + while (retries--) { + tapstatus = get_tapstatus(t); + LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus); + if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT))) + return ERROR_OK; } + + LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32 + , __func__, tapstatus); + return ERROR_FAIL; } static int exit_probemode(struct target *t) @@ -498,6 +491,12 @@ static int halt_prep(struct target *t) if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR); + if (write_hw_reg(t, CSB, PM_DSB, 0) != ERROR_OK) + return ERROR_FAIL; + LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB); + if (write_hw_reg(t, CSL, PM_DSL, 0) != ERROR_OK) + return ERROR_FAIL; + LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL); if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7); @@ -511,8 +510,7 @@ static int halt_prep(struct target *t) LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags, eflags & EFLAGS_VM86 ? 1 : 0, eflags & EFLAGS_IF ? 1 : 0); - if (eflags & EFLAGS_VM86 - || eflags & EFLAGS_IF) { + if ((eflags & EFLAGS_VM86) || (eflags & EFLAGS_IF)) { x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF); if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK) return ERROR_FAIL; @@ -530,14 +528,14 @@ static int halt_prep(struct target *t) LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]); } if (ssar & SSAR_DPL) { - x86_32->pm_regs[I(SSAR)] = ssar & ~CSAR_DPL; + x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL; if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]); } - /* if cache's are enabled, disable and flush */ - if (!(cr0 & CR0_CD)) { + /* if cache's are enabled, disable and flush, depending on the core version */ + if (!(x86_32->core_type == LMT3_5) && !(cr0 & CR0_CD)) { LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0); if (cr0 & CR0_PG) { x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG; @@ -563,6 +561,13 @@ static int do_halt(struct target *t) t->state = TARGET_DEBUG_RUNNING; if (enter_probemode(t) != ERROR_OK) return ERROR_FAIL; + + return lakemont_update_after_probemode_entry(t); +} + +/* we need to expose the update to be able to complete the reset at SoC level */ +int lakemont_update_after_probemode_entry(struct target *t) +{ if (save_context(t) != ERROR_OK) return ERROR_FAIL; if (halt_prep(t) != ERROR_OK) @@ -595,7 +600,7 @@ static int read_all_core_hw_regs(struct target *t) unsigned i; struct x86_32_common *x86_32 = target_to_x86_32(t); for (i = 0; i < (x86_32->cache->num_regs); i++) { - if (NOT_AVAIL_REG == regs[i].pm_idx) + if (regs[i].pm_idx == NOT_AVAIL_REG) continue; err = read_hw_reg(t, regs[i].id, ®val, 1); if (err != ERROR_OK) { @@ -614,7 +619,7 @@ static int write_all_core_hw_regs(struct target *t) unsigned i; struct x86_32_common *x86_32 = target_to_x86_32(t); for (i = 0; i < (x86_32->cache->num_regs); i++) { - if (NOT_AVAIL_REG == regs[i].pm_idx) + if (regs[i].pm_idx == NOT_AVAIL_REG) continue; err = write_hw_reg(t, i, 0, 1); if (err != ERROR_OK) { @@ -633,7 +638,7 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach struct x86_32_common *x86_32 = target_to_x86_32(t); struct lakemont_core_reg *arch_info; arch_info = x86_32->cache->reg_list[reg].arch_info; - x86_32->flush = 0; /* dont flush scans till we have a batch */ + x86_32->flush = 0; /* don't flush scans till we have a batch */ if (submit_reg_pir(t, reg) != ERROR_OK) return ERROR_FAIL; if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK) @@ -651,8 +656,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach *regval = buf_get_u32(scan.out, 0, 32); if (cache) { buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval); - x86_32->cache->reg_list[reg].valid = 1; - x86_32->cache->reg_list[reg].dirty = 0; + x86_32->cache->reg_list[reg].valid = true; + x86_32->cache->reg_list[reg].dirty = false; } LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32, x86_32->cache->reg_list[reg].name, @@ -677,24 +682,24 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach arch_info->op, regval); + x86_32->flush = 0; /* don't flush scans till we have a batch */ + if (submit_reg_pir(t, reg) != ERROR_OK) + return ERROR_FAIL; + if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK) + return ERROR_FAIL; scan.out[0] = RDWRPDR; - x86_32->flush = 0; /* dont flush scans till we have a batch */ if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK) return ERROR_FAIL; - if (submit_reg_pir(t, reg) != ERROR_OK) - return ERROR_FAIL; - if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK) - return ERROR_FAIL; x86_32->flush = 1; if (submit_instruction_pir(t, PDR2SRAM) != ERROR_OK) return ERROR_FAIL; /* we are writing from the cache so ensure we reset flags */ if (cache) { - x86_32->cache->reg_list[reg].dirty = 0; - x86_32->cache->reg_list[reg].valid = 0; + x86_32->cache->reg_list[reg].dirty = false; + x86_32->cache->reg_list[reg].valid = false; } return ERROR_OK; } @@ -924,15 +929,15 @@ int lakemont_poll(struct target *t) */ struct breakpoint *bp = NULL; bp = breakpoint_find(t, eip-1); - if (bp != NULL) { + if (bp) { t->debug_reason = DBG_REASON_BREAKPOINT; if (bp->type == BKPT_SOFT) { - /* The EIP is now pointing the the next byte after the + /* The EIP is now pointing the next byte after the * breakpoint instruction. This needs to be corrected. */ buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1); - x86_32->cache->reg_list[EIP].dirty = 1; - x86_32->cache->reg_list[EIP].valid = 1; + x86_32->cache->reg_list[EIP].dirty = true; + x86_32->cache->reg_list[EIP].valid = true; LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1); } else { /* it's not a hardware breakpoint (checked already in DR6 state) @@ -954,6 +959,7 @@ int lakemont_poll(struct target *t) return target_call_event_callbacks(t, TARGET_EVENT_HALTED); } } + return ERROR_OK; } @@ -982,7 +988,7 @@ int lakemont_halt(struct target *t) } } -int lakemont_resume(struct target *t, int current, uint32_t address, +int lakemont_resume(struct target *t, int current, target_addr_t address, int handle_breakpoints, int debug_execution) { struct breakpoint *bp = NULL; @@ -996,7 +1002,7 @@ int lakemont_resume(struct target *t, int current, uint32_t address, /* running away for a software breakpoint needs some special handling */ uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32); bp = breakpoint_find(t, eip); - if (bp != NULL /*&& bp->type == BKPT_SOFT*/) { + if (bp /*&& bp->type == BKPT_SOFT*/) { /* the step will step over the breakpoint */ if (lakemont_step(t, 0, 0, 1) != ERROR_OK) { LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " " @@ -1007,12 +1013,12 @@ int lakemont_resume(struct target *t, int current, uint32_t address, /* if breakpoints are enabled, we need to redirect these into probe mode */ struct breakpoint *activeswbp = t->breakpoints; - while (activeswbp != NULL && activeswbp->set == 0) + while (activeswbp && !activeswbp->is_set) activeswbp = activeswbp->next; struct watchpoint *activehwbp = t->watchpoints; - while (activehwbp != NULL && activehwbp->set == 0) + while (activehwbp && !activehwbp->is_set) activehwbp = activehwbp->next; - if (activeswbp != NULL || activehwbp != NULL) + if (activeswbp || activehwbp) buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1); if (do_resume(t) != ERROR_OK) return ERROR_FAIL; @@ -1024,7 +1030,7 @@ int lakemont_resume(struct target *t, int current, uint32_t address, } int lakemont_step(struct target *t, int current, - uint32_t address, int handle_breakpoints) + target_addr_t address, int handle_breakpoints) { struct x86_32_common *x86_32 = target_to_x86_32(t); uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32); @@ -1037,7 +1043,7 @@ int lakemont_step(struct target *t, int current, if (check_not_halted(t)) return ERROR_TARGET_NOT_HALTED; bp = breakpoint_find(t, eip); - if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) { + if (retval == ERROR_OK && bp/*&& bp->type == BKPT_SOFT*/) { /* TODO: This should only be done for software breakpoints. * Stepping from hardware breakpoints should be possible with the resume flag * Needs testing. @@ -1053,7 +1059,8 @@ int lakemont_step(struct target *t, int current, LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32, eflags, pmcr, eip); - tapstatus = get_tapstatus(t); + /* Returned value unused. Can this line be removed? */ + get_tapstatus(t); t->debug_reason = DBG_REASON_SINGLESTEP; t->state = TARGET_DEBUG_RUNNING; @@ -1088,7 +1095,7 @@ int lakemont_step(struct target *t, int current, /* try to re-apply the breakpoint, even of step failed * TODO: When a bp was set, we should try to stop the target - fix the return above */ - if (bp != NULL/*&& bp->type == BKPT_SOFT*/) { + if (bp/*&& bp->type == BKPT_SOFT*/) { /* TODO: This should only be done for software breakpoints. * Stepping from hardware breakpoints should be possible with the resume flag * Needs testing. @@ -1099,15 +1106,137 @@ int lakemont_step(struct target *t, int current, return retval; } -/* TODO - implement resetbreak fully through CLTAP registers */ +static int lakemont_reset_break(struct target *t) +{ + struct x86_32_common *x86_32 = target_to_x86_32(t); + struct jtag_tap *saved_tap = x86_32->curr_tap; + struct scan_field *fields = &scan.field; + + int retval = ERROR_OK; + + LOG_DEBUG("issuing port 0xcf9 reset"); + + /* prepare resetbreak setting the proper bits in CLTAPC_CPU_VPREQ */ + x86_32->curr_tap = jtag_tap_by_position(1); + if (!x86_32->curr_tap) { + x86_32->curr_tap = saved_tap; + LOG_ERROR("%s could not select quark_x10xx.cltap", __func__); + return ERROR_FAIL; + } + + fields->in_value = NULL; + fields->num_bits = 8; + + /* select CLTAPC_CPU_VPREQ instruction*/ + scan.out[0] = 0x51; + fields->out_value = ((uint8_t *)scan.out); + jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + x86_32->curr_tap = saved_tap; + LOG_ERROR("%s irscan failed to execute queue", __func__); + return retval; + } + + /* set enable_preq_on_reset & enable_preq_on_reset2 bits*/ + scan.out[0] = 0x06; + fields->out_value = ((uint8_t *)scan.out); + jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + LOG_ERROR("%s drscan failed to execute queue", __func__); + x86_32->curr_tap = saved_tap; + return retval; + } + + /* restore current tap */ + x86_32->curr_tap = saved_tap; + + return ERROR_OK; +} + +/* + * If we ever get an adapter with support for PREQ# and PRDY#, we should + * update this function to add support for using those two signals. + * + * Meanwhile, we're assuming that we only support reset break. + */ int lakemont_reset_assert(struct target *t) { - LOG_DEBUG("-"); + struct x86_32_common *x86_32 = target_to_x86_32(t); + /* write 0x6 to I/O port 0xcf9 to cause the reset */ + uint8_t cf9_reset_val = 0x6; + int retval; + + LOG_DEBUG(" "); + + if (t->state != TARGET_HALTED) { + LOG_DEBUG("target must be halted first"); + retval = lakemont_halt(t); + if (retval != ERROR_OK) { + LOG_ERROR("could not halt target"); + return retval; + } + x86_32->forced_halt_for_reset = true; + } + + if (t->reset_halt) { + retval = lakemont_reset_break(t); + if (retval != ERROR_OK) + return retval; + } + + retval = x86_32_common_write_io(t, 0xcf9, BYTE, &cf9_reset_val); + if (retval != ERROR_OK) { + LOG_ERROR("could not write to port 0xcf9"); + return retval; + } + + if (!t->reset_halt && x86_32->forced_halt_for_reset) { + x86_32->forced_halt_for_reset = false; + retval = lakemont_resume(t, true, 0x00, false, true); + if (retval != ERROR_OK) + return retval; + } + + /* remove breakpoints and watchpoints */ + x86_32_common_reset_breakpoints_watchpoints(t); + return ERROR_OK; } int lakemont_reset_deassert(struct target *t) { - LOG_DEBUG("-"); + int retval; + + LOG_DEBUG(" "); + + if (target_was_examined(t)) { + retval = lakemont_poll(t); + if (retval != ERROR_OK) + return retval; + } + + if (t->reset_halt) { + /* entered PM after reset, update the state */ + retval = lakemont_update_after_probemode_entry(t); + if (retval != ERROR_OK) { + LOG_ERROR("could not update state after probemode entry"); + return retval; + } + + if (t->state != TARGET_HALTED) { + LOG_WARNING("%s: ran after reset and before halt ...", + target_name(t)); + if (target_was_examined(t)) { + retval = target_halt(t); + if (retval != ERROR_OK) + return retval; + } else { + t->state = TARGET_UNKNOWN; + } + } + } + return ERROR_OK; }