X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fhla_target.c;h=d3a16cd9b8194d902ce0147e2854d3f11314a023;hb=0c6e0bb82bef9c93506e2f30fc20918691540e65;hp=efc03130d74dfdf16cdeb64b577606828e757577;hpb=1e6970dafdccfec388d1a816c2019f9c6b26e338;p=fw%2Fopenocd diff --git a/src/target/hla_target.c b/src/target/hla_target.c index efc03130d..d3a16cd9b 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2011 by Mathias Kuester * * Mathias Kuester * @@ -6,27 +8,13 @@ * spen@spen-soft.co.uk * * * * revised: 4/25/13 by brent@mbari.org [DCC target request support] * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H #include "config.h" #endif +#include "jtag/interface.h" #include "jtag/jtag.h" #include "jtag/hla/hla_transport.h" #include "jtag/hla/hla_interface.h" @@ -38,10 +26,12 @@ #include "target_type.h" #include "armv7m.h" #include "cortex_m.h" +#include "arm_adi_v5.h" #include "arm_semihosting.h" #include "target_request.h" +#include -#define savedDCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */ +#define SAVED_DCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */ #define ARMV7M_SCS_DCRSR DCB_DCRSR #define ARMV7M_SCS_DCRDR DCB_DCRDR @@ -52,198 +42,17 @@ static inline struct hl_interface_s *target_to_adapter(struct target *target) } static int adapter_load_core_reg_u32(struct target *target, - uint32_t num, uint32_t *value) + uint32_t regsel, uint32_t *value) { - int retval; struct hl_interface_s *adapter = target_to_adapter(target); - - LOG_DEBUG("%s", __func__); - - /* NOTE: we "know" here that the register identifiers used - * in the v7m header match the Cortex-M3 Debug Core Register - * Selector values for R0..R15, xPSR, MSP, and PSP. - */ - switch (num) { - case 0 ... 18: - /* read a normal core register */ - retval = adapter->layout->api->read_reg(adapter->handle, num, value); - - if (retval != ERROR_OK) { - LOG_ERROR("JTAG failure %i", retval); - return ERROR_JTAG_DEVICE_ERROR; - } - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); - break; - - case ARMV7M_FPSID: - case ARMV7M_FPEXC: - *value = 0; - break; - - case ARMV7M_FPSCR: - /* Floating-point Status and Registers */ - retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33); - if (retval != ERROR_OK) - return retval; - retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); - break; - - case ARMV7M_S0 ... ARMV7M_S31: - /* Floating-point Status and Registers */ - retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64); - if (retval != ERROR_OK) - return retval; - retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); - break; - - case ARMV7M_D0 ... ARMV7M_D15: - value = 0; - break; - - case ARMV7M_PRIMASK: - case ARMV7M_BASEPRI: - case ARMV7M_FAULTMASK: - case ARMV7M_CONTROL: - /* Cortex-M3 packages these four registers as bitfields - * in one Debug Core register. So say r0 and r2 docs; - * it was removed from r1 docs, but still works. - */ - retval = adapter->layout->api->read_reg(adapter->handle, 20, value); - if (retval != ERROR_OK) - return retval; - - switch (num) { - case ARMV7M_PRIMASK: - *value = buf_get_u32((uint8_t *) value, 0, 1); - break; - - case ARMV7M_BASEPRI: - *value = buf_get_u32((uint8_t *) value, 8, 8); - break; - - case ARMV7M_FAULTMASK: - *value = buf_get_u32((uint8_t *) value, 16, 1); - break; - - case ARMV7M_CONTROL: - *value = buf_get_u32((uint8_t *) value, 24, 2); - break; - } - - LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", - (int)num, *value); - break; - - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - - return ERROR_OK; + return adapter->layout->api->read_reg(adapter->handle, regsel, value); } static int adapter_store_core_reg_u32(struct target *target, - uint32_t num, uint32_t value) + uint32_t regsel, uint32_t value) { - int retval; - uint32_t reg; - struct armv7m_common *armv7m = target_to_armv7m(target); struct hl_interface_s *adapter = target_to_adapter(target); - - LOG_DEBUG("%s", __func__); - - /* NOTE: we "know" here that the register identifiers used - * in the v7m header match the Cortex-M3 Debug Core Register - * Selector values for R0..R15, xPSR, MSP, and PSP. - */ - switch (num) { - case 0 ... 18: - retval = adapter->layout->api->write_reg(adapter->handle, num, value); - - if (retval != ERROR_OK) { - struct reg *r; - - LOG_ERROR("JTAG failure"); - r = armv7m->arm.core_cache->reg_list + num; - r->dirty = r->valid; - return ERROR_JTAG_DEVICE_ERROR; - } - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - break; - - case ARMV7M_FPSID: - case ARMV7M_FPEXC: - break; - - case ARMV7M_FPSCR: - /* Floating-point Status and Registers */ - retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value); - if (retval != ERROR_OK) - return retval; - retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16)); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - break; - - case ARMV7M_S0 ... ARMV7M_S31: - /* Floating-point Status and Registers */ - retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value); - if (retval != ERROR_OK) - return retval; - retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16)); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - break; - - case ARMV7M_D0 ... ARMV7M_D15: - break; - - case ARMV7M_PRIMASK: - case ARMV7M_BASEPRI: - case ARMV7M_FAULTMASK: - case ARMV7M_CONTROL: - /* Cortex-M3 packages these four registers as bitfields - * in one Debug Core register. So say r0 and r2 docs; - * it was removed from r1 docs, but still works. - */ - - adapter->layout->api->read_reg(adapter->handle, 20, ®); - - switch (num) { - case ARMV7M_PRIMASK: - buf_set_u32((uint8_t *) ®, 0, 1, value); - break; - - case ARMV7M_BASEPRI: - buf_set_u32((uint8_t *) ®, 8, 8, value); - break; - - case ARMV7M_FAULTMASK: - buf_set_u32((uint8_t *) ®, 16, 1, value); - break; - - case ARMV7M_CONTROL: - buf_set_u32((uint8_t *) ®, 24, 2, value); - break; - } - - adapter->layout->api->write_reg(adapter->handle, 20, reg); - - LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - break; - - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - - return ERROR_OK; + return adapter->layout->api->write_reg(adapter->handle, regsel, value); } static int adapter_examine_debug_reason(struct target *target) @@ -287,7 +96,10 @@ static int hl_target_request_data(struct target *target, uint32_t i; for (i = 0; i < (size * 4); i++) { - hl_dcc_read(hl_if, &data, &ctrl); + int err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + buffer[i] = data; } @@ -297,6 +109,8 @@ static int hl_target_request_data(struct target *target, static int hl_handle_target_request(void *priv) { struct target *target = priv; + int err; + if (!target_was_examined(target)) return ERROR_OK; struct hl_interface_s *hl_if = target_to_adapter(target); @@ -308,7 +122,9 @@ static int hl_handle_target_request(void *priv) uint8_t data; uint8_t ctrl; - hl_dcc_read(hl_if, &data, &ctrl); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; /* check if we have data */ if (ctrl & (1 << 0)) { @@ -316,11 +132,20 @@ static int hl_handle_target_request(void *priv) /* we assume target is quick enough */ request = data; - hl_dcc_read(hl_if, &data, &ctrl); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + request |= (data << 8); - hl_dcc_read(hl_if, &data, &ctrl); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + request |= (data << 16); - hl_dcc_read(hl_if, &data, &ctrl); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + request |= (data << 24); target_request(target, request); } @@ -344,9 +169,10 @@ static int adapter_init_arch_info(struct target *target, armv7m->store_core_reg_u32 = adapter_store_core_reg_u32; armv7m->examine_debug_reason = adapter_examine_debug_reason; - armv7m->stlink = true; + armv7m->is_hla_target = true; - target_register_timer_callback(hl_handle_target_request, 1, 1, target); + target_register_timer_callback(hl_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); return ERROR_OK; } @@ -357,7 +183,7 @@ static int adapter_init_target(struct command_context *cmd_ctx, LOG_DEBUG("%s", __func__); armv7m_build_reg_cache(target); - + arm_semihosting_init(target); return ERROR_OK; } @@ -365,11 +191,19 @@ static int adapter_target_create(struct target *target, Jim_Interp *interp) { LOG_DEBUG("%s", __func__); + struct adiv5_private_config *pc = target->private_config; + if (pc && pc->ap_num != DP_APSEL_INVALID && pc->ap_num != 0) { + LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)"); + return ERROR_COMMAND_SYNTAX_ERROR; + } struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common)); + if (!cortex_m) { + LOG_ERROR("No memory creating target"); + return ERROR_FAIL; + } - if (!cortex_m) - return ERROR_COMMAND_SYNTAX_ERROR; + cortex_m->common_magic = CORTEX_M_COMMON_MAGIC; adapter_init_arch_info(target, cortex_m, target->tap); @@ -384,7 +218,7 @@ static int adapter_load_context(struct target *target) for (int i = 0; i < num_regs; i++) { struct reg *r = &armv7m->arm.core_cache->reg_list[i]; - if (!r->valid) + if (r->exist && !r->valid) armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY); } @@ -397,11 +231,11 @@ static int adapter_debug_entry(struct target *target) struct armv7m_common *armv7m = target_to_armv7m(target); struct arm *arm = &armv7m->arm; struct reg *r; - uint32_t xPSR; + uint32_t xpsr; int retval; /* preserve the DCRDR across halts */ - retval = target_read_u32(target, DCB_DCRDR, &target->savedDCRDR); + retval = target_read_u32(target, DCB_DCRDR, &target->SAVED_DCRDR); if (retval != ERROR_OK) return retval; @@ -415,17 +249,17 @@ static int adapter_debug_entry(struct target *target) adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA); r = arm->cpsr; - xPSR = buf_get_u32(r->value, 0, 32); + xpsr = buf_get_u32(r->value, 0, 32); /* Are we in an exception handler */ - if (xPSR & 0x1FF) { - armv7m->exception_number = (xPSR & 0x1FF); + if (xpsr & 0x1FF) { + armv7m->exception_number = (xpsr & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { unsigned control = buf_get_u32(arm->core_cache - ->reg_list[ARMV7M_CONTROL].value, 0, 2); + ->reg_list[ARMV7M_CONTROL].value, 0, 3); /* is this thread privileged? */ arm->core_mode = control & 1 @@ -443,7 +277,7 @@ static int adapter_debug_entry(struct target *target) LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s", arm_mode_name(arm->core_mode), - *(uint32_t *)(arm->pc->value), + buf_get_u32(arm->pc->value, 0, 32), target_state_name(target)); return retval; @@ -466,6 +300,9 @@ static int adapter_poll(struct target *target) if (prev_target_state == state) return ERROR_OK; + if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING) + return ERROR_OK; + target->state = state; if (state == TARGET_HALTED) { @@ -489,7 +326,7 @@ static int adapter_poll(struct target *target) return ERROR_OK; } -static int adapter_assert_reset(struct target *target) +static int hl_assert_reset(struct target *target) { int res = ERROR_OK; struct hl_interface_s *adapter = target_to_adapter(target); @@ -504,8 +341,7 @@ static int adapter_assert_reset(struct target *target) if ((jtag_reset_config & RESET_HAS_SRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { - jtag_add_reset(0, 1); - res = adapter->layout->api->assert_srst(adapter->handle, 0); + res = adapter_assert_reset(); srst_asserted = true; } @@ -519,8 +355,7 @@ static int adapter_assert_reset(struct target *target) if (jtag_reset_config & RESET_HAS_SRST) { if (!srst_asserted) { - jtag_add_reset(0, 1); - res = adapter->layout->api->assert_srst(adapter->handle, 0); + res = adapter_assert_reset(); } if (res == ERROR_COMMAND_NOTFOUND) LOG_ERROR("Hardware srst not supported, falling back to software reset"); @@ -553,23 +388,16 @@ static int adapter_assert_reset(struct target *target) return ERROR_OK; } -static int adapter_deassert_reset(struct target *target) +static int hl_deassert_reset(struct target *target) { - struct hl_interface_s *adapter = target_to_adapter(target); - enum reset_types jtag_reset_config = jtag_get_reset_config(); LOG_DEBUG("%s", __func__); if (jtag_reset_config & RESET_HAS_SRST) - adapter->layout->api->assert_srst(adapter->handle, 1); - - /* virtual deassert reset, we need it for the internal - * jtag state machine - */ - jtag_add_reset(0, 0); + adapter_deassert_reset(); - target->savedDCRDR = 0; /* clear both DCC busy bits on initial resume */ + target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */ return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0); } @@ -600,7 +428,7 @@ static int adapter_halt(struct target *target) } static int adapter_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, + target_addr_t address, int handle_breakpoints, int debug_execution) { int res; @@ -610,8 +438,8 @@ static int adapter_resume(struct target *target, int current, struct breakpoint *breakpoint = NULL; struct reg *pc; - LOG_DEBUG("%s %d 0x%08" PRIx32 " %d %d", __func__, current, address, - handle_breakpoints, debug_execution); + LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current, + address, handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -645,8 +473,8 @@ static int adapter_resume(struct target *target, int current, armv7m_restore_context(target); - /* restore savedDCRDR */ - res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR); + /* restore SAVED_DCRDR */ + res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR); if (res != ERROR_OK) return res; @@ -658,7 +486,7 @@ static int adapter_resume(struct target *target, int current, /* Single step past breakpoint at current address */ breakpoint = breakpoint_find(target, resume_pc); if (breakpoint) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")", + LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")", breakpoint->address, breakpoint->unique_id); cortex_m_unset_breakpoint(target, breakpoint); @@ -691,7 +519,7 @@ static int adapter_resume(struct target *target, int current, } static int adapter_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + target_addr_t address, int handle_breakpoints) { int res; struct hl_interface_s *adapter = target_to_adapter(target); @@ -728,8 +556,8 @@ static int adapter_step(struct target *target, int current, armv7m_restore_context(target); - /* restore savedDCRDR */ - res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR); + /* restore SAVED_DCRDR */ + res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR); if (res != ERROR_OK) return res; @@ -754,7 +582,7 @@ static int adapter_step(struct target *target, int current, return ERROR_OK; } -static int adapter_read_memory(struct target *target, uint32_t address, +static int adapter_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { @@ -763,12 +591,13 @@ static int adapter_read_memory(struct target *target, uint32_t address, if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08" PRIx32 " %" PRIu32 " %" PRIu32, __func__, address, size, count); + LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32, + __func__, address, size, count); return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer); } -static int adapter_write_memory(struct target *target, uint32_t address, +static int adapter_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { @@ -777,38 +606,52 @@ static int adapter_write_memory(struct target *target, uint32_t address, if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08" PRIx32 " %" PRIu32 " %" PRIu32, __func__, address, size, count); + LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32, + __func__, address, size, count); return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer); } -static const struct command_registration adapter_command_handlers[] = { +static const struct command_registration hla_command_handlers[] = { { .chain = arm_command_handlers, }, + { + .chain = armv7m_trace_command_handlers, + }, + { + .chain = rtt_target_command_handlers, + }, + /* START_DEPRECATED_TPIU */ + { + .chain = arm_tpiu_deprecated_command_handlers, + }, + /* END_DEPRECATED_TPIU */ COMMAND_REGISTRATION_DONE }; struct target_type hla_target = { .name = "hla_target", - .deprecated_name = "stm32_stlink", .init_target = adapter_init_target, + .deinit_target = cortex_m_deinit_target, .target_create = adapter_target_create, + .target_jim_configure = adiv5_jim_configure, .examine = cortex_m_examine, - .commands = adapter_command_handlers, + .commands = hla_command_handlers, .poll = adapter_poll, .arch_state = armv7m_arch_state, .target_request_data = hl_target_request_data, - .assert_reset = adapter_assert_reset, - .deassert_reset = adapter_deassert_reset, + .assert_reset = hl_assert_reset, + .deassert_reset = hl_deassert_reset, .halt = adapter_halt, .resume = adapter_resume, .step = adapter_step, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = armv7m_get_gdb_reg_list, .read_memory = adapter_read_memory, @@ -824,4 +667,5 @@ struct target_type hla_target = { .remove_breakpoint = cortex_m_remove_breakpoint, .add_watchpoint = cortex_m_add_watchpoint, .remove_watchpoint = cortex_m_remove_watchpoint, + .profiling = cortex_m_profiling, };