X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=7e3e29911235c15db1a5dd72b597d715a99b8f73;hb=f876d5e9c769a288faa7fd14b7bf373363542aab;hp=92d2aa00968bd9d6606dcc58453f6585bd1edd4e;hpb=c45de8073d027f1a4d39640dc140666f27960e3b;p=fw%2Fopenocd diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 92d2aa009..7e3e29911 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -22,7 +22,7 @@ ***************************************************************************/ /* - * Marvell Feroceon (88F5182, 88F5281) support. + * Marvell Feroceon support, including Orion and Kirkwood SOCs. * * The Feroceon core mimics the ARM926 ICE interface with the following * differences: @@ -50,15 +50,12 @@ #endif #include "arm926ejs.h" -#include "jtag.h" -#include "log.h" +#include "target_type.h" -#include -#include int feroceon_examine(struct target_s *target); int feroceon_target_create(struct target_s *target, Jim_Interp *interp); -int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); +int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer); int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int feroceon_quit(void); @@ -118,16 +115,16 @@ target_type_t feroceon_target = int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) { scan_field_t fields[3]; - u8 out_buf[4]; - u8 instr_buf[4]; - u8 sysspeed_buf = 0x0; + uint8_t out_buf[4]; + uint8_t instr_buf[4]; + uint8_t sysspeed_buf = 0x0; /* prepare buffer */ buf_set_u32(out_buf, 0, 32, 0); buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -135,36 +132,36 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; - fields[0].out_mask = NULL; + fields[0].in_value = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; + + + + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; - fields[1].out_mask = NULL; + fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; + + + + fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; - fields[2].out_mask = NULL; + fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; + + + + - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); - /* no jtag_add_runtest(0, -1) here */ + /* no jtag_add_runtest(0, jtag_get_end_state()) here */ return ERROR_OK; } @@ -242,8 +239,8 @@ void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf arm_jtag_t *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; u32 *buf_u32 = buffer; - u16 *buf_u16 = buffer; - u8 *buf_u8 = buffer; + uint16_t *buf_u16 = buffer; + uint8_t *buf_u8 = buffer; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -335,7 +332,7 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) +void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -510,14 +507,14 @@ int feroceon_examine_debug_reason(target_t *target) return ERROR_OK; } -int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; enum armv4_5_state core_state = armv4_5->core_state; u32 x, flip, shift, save[7]; - int i; + u32 i; /* * We can't use the dcc flow control bits, so let's transfer data @@ -547,21 +544,21 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf 0xeafffff3, /* b 3b */ }; - int dcc_size = sizeof(dcc_code); + u32 dcc_size = sizeof(dcc_code); if (!arm7_9->dcc_downloads) - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); /* regrab previously allocated working_area, or allocate a new one */ if (!arm7_9->dcc_working_area) { - u8 dcc_code_buf[dcc_size]; + uint8_t dcc_code_buf[dcc_size]; /* make sure we have a working area */ if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); } /* copy target instructions to target endianness */ @@ -569,7 +566,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); /* write DCC code to working area */ - if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK) + if((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) { return retval; } @@ -645,7 +642,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) arm7_9_common_t *arm7_9; arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant); + arm926ejs_init_arch_info(target, arm926ejs, target->tap); armv4_5 = target->arch_info; arm7_9 = armv4_5->arch_info; @@ -684,7 +681,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } - int feroceon_examine(struct target_s *target) { armv4_5_common_t *armv4_5;