X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=1e7eb0961fbd4876a979e9b5767e3c8e0005fc38;hb=382148e4dd437978997d668f6ec715ddcec1c46e;hp=acaa1b3b4846cab63523783a1871cae2c75909c3;hpb=ff5ec942d80a34e20b5a3ca3328f7e6a55fb309b;p=fw%2Fopenocd diff --git a/src/target/feroceon.c b/src/target/feroceon.c index acaa1b3b4..1e7eb0961 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -1,24 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. * * Written by Nicolas Pitre * * * * Copyright (C) 2008 by Hongtao Zheng * * hontor@126.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ /* @@ -39,7 +26,7 @@ * - asserting DBGRQ doesn't work if target is looping on the undef vector * * - the EICE version signature in the COMMS_CTL reg is next to the flow bits - * not at the top, and rather meaningless due to existing discrepencies + * not at the top, and rather meaningless due to existing discrepancies * * - the DCC channel is half duplex (only one FIFO for both directions) with * seemingly no proper flow control. @@ -64,6 +51,13 @@ static int feroceon_assert_reset(struct target *target) struct arm7_9_common *arm7_9 = arm->arch_info; int ud = arm7_9->use_dbgrq; + /* TODO: apply hw reset signal in not examined state */ + if (!(target_was_examined(target))) { + LOG_WARNING("Reset is not asserted because the target is not examined."); + LOG_WARNING("Use a reset button or power cycle the target."); + return ERROR_TARGET_NOT_EXAMINED; + } + arm7_9->use_dbgrq = 0; if (target->reset_halt) arm7_9_halt(target); @@ -88,7 +82,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; @@ -368,14 +362,14 @@ static void feroceon_branch_resume_thumb(struct target *target) } static int feroceon_read_cp15(struct target *target, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) + uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value) { struct arm *arm = target->arch_info; struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; - arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, crn, crm, op2), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); err = arm7_9_execute_sys_speed(target); if (err != ERROR_OK) @@ -391,7 +385,7 @@ static int feroceon_read_cp15(struct target *target, uint32_t op1, } static int feroceon_write_cp15(struct target *target, uint32_t op1, - uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) + uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value) { struct arm *arm = target->arch_info; struct arm7_9_common *arm7_9 = arm->arch_info; @@ -405,7 +399,7 @@ static int feroceon_write_cp15(struct target *target, uint32_t op1, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, crn, crm, op2), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); return arm7_9_execute_sys_speed(target); } @@ -455,7 +449,7 @@ static int feroceon_examine_debug_reason(struct target *target) } static int feroceon_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, const uint8_t *buffer) + target_addr_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm *arm = target->arch_info; @@ -510,8 +504,7 @@ static int feroceon_bulk_write_memory(struct target *target, } /* copy target instructions to target endianness */ - for (i = 0; i < dcc_size/4; i++) - target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); + target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code); /* write DCC code to working area, using the non-optimized * memory write to avoid ending up here again */ @@ -528,8 +521,8 @@ static int feroceon_bulk_write_memory(struct target *target, /* set up target address in r0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); - arm->core_cache->reg_list[0].valid = 1; - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].valid = true; + arm->core_cache->reg_list[0].dirty = true; arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); @@ -561,7 +554,7 @@ static int feroceon_bulk_write_memory(struct target *target, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," - " expected end address 0x%08" PRIx32 + " expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "", address + count*4, endaddress); retval = ERROR_FAIL; @@ -571,12 +564,12 @@ static int feroceon_bulk_write_memory(struct target *target, /* restore target state */ for (i = 0; i <= 5; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); - arm->core_cache->reg_list[i].valid = 1; - arm->core_cache->reg_list[i].dirty = 1; + arm->core_cache->reg_list[i].valid = true; + arm->core_cache->reg_list[i].dirty = true; } buf_set_u32(arm->pc->value, 0, 32, save[i]); - arm->pc->valid = 1; - arm->pc->dirty = 1; + arm->pc->valid = true; + arm->pc->dirty = true; arm->core_state = core_state; return retval; @@ -589,6 +582,11 @@ static int feroceon_init_target(struct command_context *cmd_ctx, return ERROR_OK; } +static void feroceon_deinit_target(struct target *target) +{ + arm9tdmi_deinit_target(target); +} + static void feroceon_common_setup(struct target *target) { struct arm *arm = target->arch_info; @@ -706,6 +704,7 @@ struct target_type feroceon_target = { .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, @@ -724,6 +723,7 @@ struct target_type feroceon_target = { .commands = arm926ejs_command_handlers, .target_create = feroceon_target_create, .init_target = feroceon_init_target, + .deinit_target = feroceon_deinit_target, .examine = feroceon_examine, }; @@ -743,6 +743,7 @@ struct target_type dragonite_target = { .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory,