X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=1d1351bbc6442ac61efe1acc9e304a9000f3090e;hb=762ddcb74948852b0dfb25fcbca0965b09249a2f;hp=3617b2be747676f08aaf1bd5f73752d1e80252de;hpb=3a550e5b5fe011e526b150a5d234b48e8e2aaad6;p=fw%2Fopenocd diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 3617b2be7..1d1351bbc 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -16,9 +16,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ /* @@ -39,7 +37,7 @@ * - asserting DBGRQ doesn't work if target is looping on the undef vector * * - the EICE version signature in the COMMS_CTL reg is next to the flow bits - * not at the top, and rather meaningless due to existing discrepencies + * not at the top, and rather meaningless due to existing discrepancies * * - the DCC channel is half duplex (only one FIFO for both directions) with * seemingly no proper flow control. @@ -58,13 +56,19 @@ #include "register.h" #include "arm_opcodes.h" - static int feroceon_assert_reset(struct target *target) { struct arm *arm = target->arch_info; struct arm7_9_common *arm7_9 = arm->arch_info; int ud = arm7_9->use_dbgrq; + /* TODO: apply hw reset signal in not examined state */ + if (!(target_was_examined(target))) { + LOG_WARNING("Reset is not asserted because the target is not examined."); + LOG_WARNING("Use a reset button or power cycle the target."); + return ERROR_TARGET_NOT_EXAMINED; + } + arm7_9->use_dbgrq = 0; if (target->reset_halt) arm7_9_halt(target); @@ -89,7 +93,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; @@ -160,7 +164,7 @@ static void feroceon_change_to_arm(struct target *target, uint32_t *r0, } static void feroceon_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm *arm = target->arch_info; @@ -180,7 +184,7 @@ static void feroceon_read_core_regs(struct target *target, } static void feroceon_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm *arm = target->arch_info; @@ -195,11 +199,9 @@ static void feroceon_read_core_regs_target_buffer(struct target *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) { - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -350,7 +352,7 @@ static void feroceon_branch_resume_thumb(struct target *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1 + arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,pc,#1 */ arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -452,15 +454,13 @@ static int feroceon_examine_debug_reason(struct target *target) { /* the MOE is not implemented */ if (target->debug_reason != DBG_REASON_SINGLESTEP) - { target->debug_reason = DBG_REASON_DBGRQ; - } return ERROR_OK; } static int feroceon_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, const uint8_t *buffer) + target_addr_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm *arm = target->arch_info; @@ -473,8 +473,7 @@ static int feroceon_bulk_write_memory(struct target *target, * We can't use the dcc flow control bits, so let's transfer data * with 31 bits and flip the MSB each time a new data word is sent. */ - static uint32_t dcc_code[] = - { + static uint32_t dcc_code[] = { 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xe3a0301e, /* 1: mov r3, #30 */ 0xe3a04002, /* mov r4, #2 */ @@ -499,30 +498,31 @@ static int feroceon_bulk_write_memory(struct target *target, uint32_t dcc_size = sizeof(dcc_code); + if (address % 4 != 0) + return ERROR_TARGET_UNALIGNED_ACCESS; + if (!arm7_9->dcc_downloads) - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* regrab previously allocated working_area, or allocate a new one */ - if (!arm7_9->dcc_working_area) - { + if (!arm7_9->dcc_working_area) { uint8_t dcc_code_buf[dcc_size]; /* make sure we have a working area */ - if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) - { + if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* copy target instructions to target endianness */ - for (i = 0; i < dcc_size/4; i++) - target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); + target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code); - /* write DCC code to working area */ - if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) - { + /* write DCC code to working area, using the non-optimized + * memory write to avoid ending up here again */ + retval = arm7_9_write_memory_no_opt(target, + arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf); + if (retval != ERROR_OK) return retval; - } } /* backup clobbered processor state */ @@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target, /* set up target address in r0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); - arm->core_cache->reg_list[0].valid = 1; - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].valid = true; + arm->core_cache->reg_list[0].dirty = true; arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); @@ -543,14 +543,12 @@ static int feroceon_bulk_write_memory(struct target *target, x = 0; flip = 0; shift = 1; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { uint32_t y = target_buffer_get_u32(target, buffer); uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = y << (32 - shift); - if (++shift >= 32 || i + 1 >= count) - { + if (++shift >= 32 || i + 1 >= count) { z = (x >> 1) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = 0; @@ -563,27 +561,26 @@ static int feroceon_bulk_write_memory(struct target *target, if (retval == ERROR_OK) retval = target_wait_state(target, TARGET_HALTED, 500); if (retval == ERROR_OK) { - uint32_t endaddress = + uint32_t endaddress = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," - " expected end address 0x%08" PRIx32 + " expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "", - address + count*4, endaddress); + address + count*4, endaddress); retval = ERROR_FAIL; } } /* restore target state */ - for (i = 0; i <= 5; i++) - { + for (i = 0; i <= 5; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); - arm->core_cache->reg_list[i].valid = 1; - arm->core_cache->reg_list[i].dirty = 1; + arm->core_cache->reg_list[i].valid = true; + arm->core_cache->reg_list[i].dirty = true; } buf_set_u32(arm->pc->value, 0, 32, save[i]); - arm->pc->valid = 1; - arm->pc->dirty = 1; + arm->pc->valid = true; + arm->pc->dirty = true; arm->core_state = core_state; return retval; @@ -596,6 +593,11 @@ static int feroceon_init_target(struct command_context *cmd_ctx, return ERROR_OK; } +static void feroceon_deinit_target(struct target *target) +{ + arm9tdmi_deinit_target(target); +} + static void feroceon_common_setup(struct target *target) { struct arm *arm = target->arch_info; @@ -616,6 +618,8 @@ static void feroceon_common_setup(struct target *target) arm7_9->enable_single_step = feroceon_enable_single_step; arm7_9->disable_single_step = feroceon_disable_single_step; + arm7_9->bulk_write_memory = feroceon_bulk_write_memory; + /* MOE is not implemented */ arm7_9->examine_debug_reason = feroceon_examine_debug_reason; @@ -631,11 +635,15 @@ static void feroceon_common_setup(struct target *target) static int feroceon_target_create(struct target *target, Jim_Interp *interp) { - struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); + struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); arm926ejs_init_arch_info(target, arm926ejs, target->tap); feroceon_common_setup(target); + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + arm7_9->write_memory = arm926ejs_write_memory; + /* the standard ARM926 methods don't always work (don't ask...) */ arm926ejs->read_cp15 = feroceon_read_cp15; arm926ejs->write_cp15 = feroceon_write_cp15; @@ -645,11 +653,15 @@ static int feroceon_target_create(struct target *target, Jim_Interp *interp) static int dragonite_target_create(struct target *target, Jim_Interp *interp) { - struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common)); + struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); arm966e_init_arch_info(target, arm966e, target->tap); feroceon_common_setup(target); + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + arm7_9->write_memory = arm7_9_write_memory; + return ERROR_OK; } @@ -687,8 +699,7 @@ static int feroceon_examine(struct target *target) return ERROR_OK; } -struct target_type feroceon_target = -{ +struct target_type feroceon_target = { .name = "feroceon", .poll = arm7_9_poll, @@ -704,11 +715,11 @@ struct target_type feroceon_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, + .write_memory = arm7_9_write_memory_opt, .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory, @@ -723,11 +734,11 @@ struct target_type feroceon_target = .commands = arm926ejs_command_handlers, .target_create = feroceon_target_create, .init_target = feroceon_init_target, + .deinit_target = feroceon_deinit_target, .examine = feroceon_examine, }; -struct target_type dragonite_target = -{ +struct target_type dragonite_target = { .name = "dragonite", .poll = arm7_9_poll, @@ -743,11 +754,11 @@ struct target_type dragonite_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, + .write_memory = arm7_9_write_memory_opt, .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory, @@ -764,4 +775,3 @@ struct target_type dragonite_target = .init_target = feroceon_init_target, .examine = feroceon_examine, }; -