X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=a38028c8004b92dc879ba564beb80d7bd683920c;hb=991ed5a2b657e660f744eefddb084724e52938ea;hp=59cd5624f0be07461eaba058718c231cebd5c521;hpb=7f6bab0c4c36d7a64f933904e5add9bc6b36d78c;p=fw%2Fopenocd

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 59cd5624f..a38028c80 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -47,6 +47,8 @@
  * core entered debug mode.
  */
 
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+
 /*
  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  */
@@ -342,10 +344,15 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* bits 31:0 -- data (ignored here) */
 	fields[0].num_bits = 32;
@@ -357,7 +364,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bits 36:32 -- register */
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = reg_addr;
+	field1_out[0] = reg_addr;
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
@@ -365,7 +372,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bit 37 -- 0/read */
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
@@ -382,7 +389,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	 * EICE_COMMS_DATA would read the register twice
 	 * reading the control register is safe
 	 */
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 	/* traverse Update-DR, reading but with no other side effects */
 	jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
@@ -403,9 +410,14 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -413,12 +425,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -429,7 +441,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 		 * to avoid reading additional data from the DCC data reg
 		 */
 		if (size == 1)
-			fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+			field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 		fields[0].in_value = (uint8_t *)data;
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -469,7 +481,7 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
 	int retval;
 
@@ -519,9 +531,14 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field0_out[4];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
@@ -529,18 +546,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 1;
+	field2_out[0] = 1;
 
 	fields[2].in_value = NULL;
 
 	while (size > 0)
 	{
-		buf_set_u32(fields[0].out_value, 0, 32, *data);
+		buf_set_u32(field0_out, 0, 32, *data);
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 		data++;
@@ -570,10 +587,17 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	else if (hsbit == EICE_COMM_CTRL_RBIT)
 		hsact = 0;
 	else
+	{
+		LOG_ERROR("Invalid arguments");
 		return ERROR_INVALID_ARGUMENTS;
+	}
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -581,12 +605,12 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -603,6 +627,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	} while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
 			+ (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
 
+	LOG_ERROR("embeddedice handshake timeout");
 	return ERROR_TARGET_TIMEOUT;
 }
 
@@ -611,7 +636,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
  * This is an inner loop of the open loop DCC write of data to target
  */
 void embeddedice_write_dcc(struct jtag_tap *tap,
-		int reg_addr, uint8_t *buffer, int little, int count)
+		int reg_addr, const uint8_t *buffer, int little, int count)
 {
 	int i;