X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=81d6ccf4f5a4ed3d69212ed3f5072a13151f7f40;hb=6663a788a53ee38f2d6950fe7802eae7855e01f3;hp=09a51b7b3b35f53996feaebe564f91d87e23ea60;hpb=7743e0fb4390d09c315ce9c6edbb2c3ba6b8c2d9;p=fw%2Fopenocd

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 09a51b7b3..81d6ccf4f 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -149,7 +149,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
 	uint32_t mask_on, uint32_t mask_off)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 
 	/* mask off status bits */
 	cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
@@ -162,7 +162,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
 static int cortex_m3_clear_halt(struct target *target)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	int retval;
 
 	/* clear step if any */
@@ -185,7 +185,7 @@ static int cortex_m3_clear_halt(struct target *target)
 static int cortex_m3_single_step_core(struct target *target)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	uint32_t dhcsr_save;
 	int retval;
 
@@ -222,7 +222,7 @@ static int cortex_m3_endreset_event(struct target *target)
 	uint32_t dcb_demcr;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common *armv7m = &cortex_m3->armv7m;
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 	struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 
@@ -334,7 +334,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
 {
 	uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	int retval;
 
 	retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
@@ -406,7 +406,7 @@ static int cortex_m3_debug_entry(struct target *target)
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common *armv7m = &cortex_m3->armv7m;
 	struct arm *arm = &armv7m->arm;
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	struct reg *r;
 
 	LOG_DEBUG(" ");
@@ -498,7 +498,7 @@ static int cortex_m3_poll(struct target *target)
 	int retval = ERROR_OK;
 	enum target_state prev_target_state = target->state;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 
 	/* Read from Debug Halting Control and Status Register */
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -629,7 +629,7 @@ static int cortex_m3_halt(struct target *target)
 static int cortex_m3_soft_reset_halt(struct target *target)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	uint32_t dcb_dhcsr = 0;
 	int retval, timeout = 0;
 
@@ -794,7 +794,7 @@ static int cortex_m3_step(struct target *target, int current,
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common *armv7m = &cortex_m3->armv7m;
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	struct breakpoint *breakpoint = NULL;
 	struct reg *pc = armv7m->arm.pc;
 	bool bkpt_inst_found = false;
@@ -934,7 +934,7 @@ static int cortex_m3_step(struct target *target, int current,
 static int cortex_m3_assert_reset(struct target *target)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
 
 	LOG_DEBUG("target->state: %s",
@@ -952,6 +952,16 @@ static int cortex_m3_assert_reset(struct target *target)
 		return ERROR_OK;
 	}
 
+	/* some cores support connecting while srst is asserted
+	 * use that mode is it has been configured */
+
+	bool srst_asserted = false;
+
+	if (jtag_reset_config & RESET_SRST_NO_GATING) {
+		adapter_assert_reset();
+		srst_asserted = true;
+	}
+
 	/* Enable debug requests */
 	int retval;
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -963,6 +973,14 @@ static int cortex_m3_assert_reset(struct target *target)
 			return retval;
 	}
 
+	/* If the processor is sleeping in a WFI or WFE instruction, the
+	 * C_HALT bit must be asserted to regain control */
+	if (cortex_m3->dcb_dhcsr & S_SLEEP) {
+		retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+		if (retval != ERROR_OK)
+			return retval;
+	}
+
 	retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 	if (retval != ERROR_OK)
 		return retval;
@@ -996,7 +1014,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	if (jtag_reset_config & RESET_HAS_SRST) {
 		/* default to asserting srst */
-		adapter_assert_reset();
+		if (!srst_asserted)
+			adapter_assert_reset();
 	} else {
 		/* Use a standard Cortex-M3 software reset mechanism.
 		 * We default to using VECRESET as it is supported on all current cores.
@@ -1014,7 +1033,7 @@ static int cortex_m3_assert_reset(struct target *target)
 
 		if (reset_config == CORTEX_M3_RESET_VECTRESET) {
 			LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
-				"handler to reset any peripherals");
+				"handler to reset any peripherals or configure hardware srst support.");
 		}
 
 		{
@@ -1418,7 +1437,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target,
 {
 	int retval;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 
 	/* NOTE:  we "know" here that the register identifiers used
 	 * in the v7m header match the Cortex-M3 Debug Core Register
@@ -1480,7 +1499,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
 	int retval;
 	uint32_t reg;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 
 #ifdef ARMV7_GDB_HACKS
 	/* If the LR register is being modified, make sure it will put us
@@ -1556,9 +1575,15 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 	uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	/* cortex_m3 handles unaligned memory access */
 	if (count && buffer) {
 		switch (size) {
@@ -1581,9 +1606,15 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 	uint32_t size, uint32_t count, const uint8_t *buffer)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
+	if (armv7m->arm.is_armv6m) {
+		/* armv6m does not handle unaligned memory access */
+		if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
+			return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
 	if (count && buffer) {
 		switch (size) {
 			case 4:
@@ -1766,12 +1797,16 @@ int cortex_m3_examine(struct target *target)
 	uint32_t cpuid, fpcr, mvfr0, mvfr1;
 	int i;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 
-	retval = ahbap_debugport_init(swjdp);
-	if (retval != ERROR_OK)
-		return retval;
+	/* stlink shares the examine handler but does not support
+	 * all its calls */
+	if (!armv7m->stlink) {
+		retval = ahbap_debugport_init(swjdp);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	if (!target_was_examined(target)) {
 		target_set_examined(target);
@@ -1797,6 +1832,14 @@ int cortex_m3_examine(struct target *target)
 				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
 				armv7m->fp_feature = FPv4_SP;
 			}
+		} else if (i == 0) {
+			/* Cortex-M0 does not support unaligned memory access */
+			armv7m->arm.is_armv6m = true;
+		}
+
+		if (i == 4 || i == 3) {
+			/* Cortex-M3/M4 has 4096 bytes autoincrement range */
+			armv7m->dap.tar_autoincr_block = (1 << 12);
 		}
 
 		/* NOTE: FPB and DWT are both optional. */
@@ -1864,7 +1907,7 @@ static int cortex_m3_target_request_data(struct target *target,
 	uint32_t size, uint8_t *buffer)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	uint8_t data;
 	uint8_t ctrl;
 	uint32_t i;
@@ -1883,7 +1926,7 @@ static int cortex_m3_handle_target_request(void *priv)
 	if (!target_was_examined(target))
 		return ERROR_OK;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
@@ -1934,8 +1977,11 @@ static int cortex_m3_init_arch_info(struct target *target,
 	/* Leave (only) generic DAP stuff for debugport_init(); */
 	armv7m->dap.jtag_info = &cortex_m3->jtag_info;
 	armv7m->dap.memaccess_tck = 8;
-	/* Cortex-M3 has 4096 bytes autoincrement range */
-	armv7m->dap.tar_autoincr_block = (1 << 12);
+
+	/* Cortex-M3/M4 has 4096 bytes autoincrement range
+	 * but set a safe default to 1024 to support Cortex-M0
+	 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
+	armv7m->dap.tar_autoincr_block = (1 << 10);
 
 	/* register arch-specific functions */
 	armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
@@ -2003,7 +2049,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct armv7m_common *armv7m = &cortex_m3->armv7m;
-	struct adiv5_dap *swjdp = &armv7m->dap;
+	struct adiv5_dap *swjdp = armv7m->arm.dap;
 	uint32_t demcr = 0;
 	int retval;