X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=5d90e3416c1b423a5c8d553e3f04cc328cdcd4cd;hb=bf1efe05bb71b7a6fe4ec1809a6aaa9b6073aede;hp=1bd473c7c0595b0de98c3ad2326aa4353a317d59;hpb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee;p=fw%2Fopenocd
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 1bd473c7c..5d90e3416 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -18,7 +18,10 @@
* michel.jaouen@stericsson.com : smp minimum support *
* *
* Copyright (C) Broadcom 2012 *
- * ehunter@broadcom.com : Cortex R4 support *
+ * ehunter@broadcom.com : Cortex-R4 support *
+ * *
+ * Copyright (C) 2013 Kamal Dasu *
+ * kdasu.kdev@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
@@ -31,13 +34,12 @@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see . *
* *
* Cortex-A8(tm) TRM, ARM DDI 0344H *
* Cortex-A9(tm) TRM, ARM DDI 0407F *
* Cortex-A4(tm) TRM, ARM DDI 0363E *
+ * Cortex-A15(tm)TRM, ARM DDI 0438C *
* *
***************************************************************************/
@@ -51,145 +53,173 @@
#include "target_request.h"
#include "target_type.h"
#include "arm_opcodes.h"
+#include "arm_semihosting.h"
+#include "jtag/swd.h"
#include
-static int cortex_a8_poll(struct target *target);
-static int cortex_a8_debug_entry(struct target *target);
-static int cortex_a8_restore_context(struct target *target, bool bpwp);
-static int cortex_a8_set_breakpoint(struct target *target,
+static int cortex_a_poll(struct target *target);
+static int cortex_a_debug_entry(struct target *target);
+static int cortex_a_restore_context(struct target *target, bool bpwp);
+static int cortex_a_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_set_context_breakpoint(struct target *target,
+static int cortex_a_set_context_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_set_hybrid_breakpoint(struct target *target,
+static int cortex_a_set_hybrid_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int cortex_a8_unset_breakpoint(struct target *target,
+static int cortex_a_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(struct target *target,
+static int cortex_a_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+static int cortex_a_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
-static int cortex_a8_mmu(struct target *target, int *enabled);
-static int cortex_a8_virt2phys(struct target *target,
- uint32_t virt, uint32_t *phys);
-static int cortex_a8_read_apb_ab_memory(struct target *target,
+static int cortex_a_mmu(struct target *target, int *enabled);
+static int cortex_a_mmu_modify(struct target *target, int enable);
+static int cortex_a_virt2phys(struct target *target,
+ target_addr_t virt, target_addr_t *phys);
+static int cortex_a_read_cpu_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
/* restore cp15_control_reg at resume */
-static int cortex_a8_restore_cp15_control_reg(struct target *target)
+static int cortex_a_restore_cp15_control_reg(struct target *target)
{
int retval = ERROR_OK;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) {
- cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
- /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */
+ if (cortex_a->cp15_control_reg != cortex_a->cp15_control_reg_curr) {
+ cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
+ /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
retval = armv7a->arm.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg);
+ cortex_a->cp15_control_reg);
}
return retval;
}
-/* check address before cortex_a8_apb read write access with mmu on
- * remove apb predictible data abort */
-static int cortex_a8_check_address(struct target *target, uint32_t address)
+/*
+ * Set up ARM core for memory access.
+ * If !phys_access, switch to SVC mode and make sure MMU is on
+ * If phys_access, switch off mmu
+ */
+static int cortex_a_prep_memaccess(struct target *target, int phys_access)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- uint32_t os_border = armv7a->armv7a_mmu.os_border;
- if ((address < os_border) &&
- (armv7a->arm.core_mode == ARM_MODE_SVC)) {
- LOG_ERROR("%x access in userspace and target in supervisor", address);
- return ERROR_FAIL;
- }
- if ((address >= os_border) &&
- (cortex_a8->curr_mode != ARM_MODE_SVC)) {
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ int mmu_enabled = 0;
+
+ if (phys_access == 0) {
dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
- cortex_a8->curr_mode = ARM_MODE_SVC;
- LOG_INFO("%x access in kernel space and target not in supervisor",
- address);
- return ERROR_OK;
+ cortex_a_mmu(target, &mmu_enabled);
+ if (mmu_enabled)
+ cortex_a_mmu_modify(target, 1);
+ if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+ /* overwrite DACR to all-manager */
+ armv7a->arm.mcr(target, 15,
+ 0, 0, 3, 0,
+ 0xFFFFFFFF);
+ }
+ } else {
+ cortex_a_mmu(target, &mmu_enabled);
+ if (mmu_enabled)
+ cortex_a_mmu_modify(target, 0);
}
- if ((address < os_border) &&
- (cortex_a8->curr_mode == ARM_MODE_SVC)) {
+ return ERROR_OK;
+}
+
+/*
+ * Restore ARM core after memory access.
+ * If !phys_access, switch to previous mode
+ * If phys_access, restore MMU setting
+ */
+static int cortex_a_post_memaccess(struct target *target, int phys_access)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+
+ if (phys_access == 0) {
+ if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+ /* restore */
+ armv7a->arm.mcr(target, 15,
+ 0, 0, 3, 0,
+ cortex_a->cp15_dacr_reg);
+ }
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
- cortex_a8->curr_mode = ARM_MODE_ANY;
+ } else {
+ int mmu_enabled = 0;
+ cortex_a_mmu(target, &mmu_enabled);
+ if (mmu_enabled)
+ cortex_a_mmu_modify(target, 1);
}
return ERROR_OK;
}
+
+
/* modify cp15_control_reg in order to enable or disable mmu for :
* - virt2phys address conversion
* - read or write memory in phys or virt address */
-static int cortex_a8_mmu_modify(struct target *target, int enable)
+static int cortex_a_mmu_modify(struct target *target, int enable)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
int retval = ERROR_OK;
+ int need_write = 0;
+
if (enable) {
/* if mmu enabled at target stop and mmu not enable */
- if (!(cortex_a8->cp15_control_reg & 0x1U)) {
+ if (!(cortex_a->cp15_control_reg & 0x1U)) {
LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
return ERROR_FAIL;
}
- if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) {
- cortex_a8->cp15_control_reg_curr |= 0x1U;
- retval = armv7a->arm.mcr(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg_curr);
+ if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) {
+ cortex_a->cp15_control_reg_curr |= 0x1U;
+ need_write = 1;
}
} else {
- if (cortex_a8->cp15_control_reg_curr & 0x4U) {
- /* data cache is active */
- cortex_a8->cp15_control_reg_curr &= ~0x4U;
- /* flush data cache armv7 function to be called */
- if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
- armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
- }
- if ((cortex_a8->cp15_control_reg_curr & 0x1U)) {
- cortex_a8->cp15_control_reg_curr &= ~0x1U;
- retval = armv7a->arm.mcr(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg_curr);
+ if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) {
+ cortex_a->cp15_control_reg_curr &= ~0x1U;
+ need_write = 1;
}
}
+
+ if (need_write) {
+ LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32,
+ enable ? "enable mmu" : "disable mmu",
+ cortex_a->cp15_control_reg_curr);
+
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a->cp15_control_reg_curr);
+ }
return retval;
}
/*
- * Cortex-A8 Basic debug access, very low level assumes state is saved
+ * Cortex-A Basic debug access, very low level assumes state is saved
*/
-static int cortex_a8_init_debug_access(struct target *target)
+static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
- uint32_t dummy;
- LOG_DEBUG(" ");
+ /* lock memory-mapped access to debug registers to prevent
+ * software interference */
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_LOCKACCESS, 0);
+ if (retval != ERROR_OK)
+ return retval;
- /* Unlocking the debug registers for modification
- * The debugport might be uninitialised so try twice */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
- if (retval != ERROR_OK) {
- /* try again */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
- if (retval == ERROR_OK)
- LOG_USER(
- "Locking debug access failed on first, but succeeded on second try.");
- }
+ /* Disable cacheline fills and force cache write-through in debug state */
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
- /* Clear Sticky Power Down status Bit in PRSR to enable access to
- the registers in the Core Power Domain */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_PRSR, &dummy);
+
+ /* Disable TLB lookup and refill/eviction in debug state */
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
@@ -198,7 +228,30 @@ static int cortex_a8_init_debug_access(struct target *target)
/* Resync breakpoint registers */
/* Since this is likely called from init or reset, update target state information*/
- return cortex_a8_poll(target);
+ return cortex_a_poll(target);
+}
+
+static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
+{
+ /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
+ * Writes final value of DSCR into *dscr. Pass force to force always
+ * reading DSCR at least once. */
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ int64_t then = timeval_ms();
+ while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
+ force = false;
+ int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read DSCR register");
+ return retval;
+ }
+ if (timeval_ms() > then + 1000) {
+ LOG_ERROR("Timeout waiting for InstrCompl=1");
+ return ERROR_FAIL;
+ }
+ }
+ return ERROR_OK;
}
/* To reduce needless round-trips, pass in a pointer to the current
@@ -206,48 +259,37 @@ static int cortex_a8_init_debug_access(struct target *target)
* value on return from this function; or DSCR_INSTR_COMP if you
* happen to know that no instruction is pending.
*/
-static int cortex_a8_exec_opcode(struct target *target,
+static int cortex_a_exec_opcode(struct target *target,
uint32_t opcode, uint32_t *dscr_p)
{
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
/* Wait for InstrCompl bit to be set */
- long long then = timeval_ms();
- while ((dscr & DSCR_INSTR_COMP) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK) {
- LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
- return retval;
- }
- if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
- return ERROR_FAIL;
- }
- }
+ retval = cortex_a_wait_instrcmpl(target, dscr_p, false);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
- then = timeval_ms();
+ int64_t then = timeval_ms();
do {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
return retval;
}
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
return ERROR_FAIL;
}
} while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
@@ -262,54 +304,52 @@ static int cortex_a8_exec_opcode(struct target *target,
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
+static int cortex_a_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t *regfile)
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
- retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+ retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
+ retval = cortex_a_dap_write_coreregister_u32(target, address, 0);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ retval = cortex_a_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_buf_u32(swjdp, armv7a->memory_ap,
- (uint8_t *)(®file[1]), 4*15, address);
+ retval = mem_ap_read_buf(armv7a->memory_ap,
+ (uint8_t *)(®file[1]), 4, 15, address);
return retval;
}
-static int cortex_a8_dap_read_coreregister_u32(struct target *target,
+static int cortex_a_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
if (reg < 15) {
/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
} else if (reg == 15) {
/* "MOV r0, r15"; then move r0 to DCCTX */
- retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+ retval = cortex_a_exec_opcode(target, 0xE1A0000F, &dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -318,10 +358,10 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
/* "MRS r0, CPSR" or "MRS r0, SPSR"
* then move r0 to DCCTX
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -329,45 +369,44 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
}
/* Wait for DTRRXfull then read DTRRTX */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
return ERROR_FAIL;
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+static int cortex_a_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
@@ -378,14 +417,14 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
- retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
if (Rd < 15) {
/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -394,29 +433,29 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0"
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ retval = cortex_a_exec_opcode(target, 0xE1A0F000, &dscr);
if (retval != ERROR_OK)
return retval;
} else {
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
&dscr);
if (retval != ERROR_OK)
return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
if (Rd == 16) {
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
if (retval != ERROR_OK)
@@ -428,21 +467,20 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(struct target *target,
+static int cortex_a_dap_write_memap_register_u32(struct target *target,
uint32_t address,
uint32_t value)
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, address, value);
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
return retval;
}
/*
- * Cortex-A8 implementation of Debug Programmer's Model
+ * Cortex-A implementation of Debug Programmer's Model
*
* NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
* so there's no need to poll for it before executing an instruction.
@@ -452,22 +490,21 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target,
* be the places to enable/disable that mode.
*/
-static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
{
- return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+ return container_of(dpm, struct cortex_a_common, armv7a_common.dpm);
}
-static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap,
- a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+ return mem_ap_write_u32(a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
-static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
@@ -475,10 +512,10 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
dscr = *dscr_p;
/* Wait for DTRRXfull */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
@@ -488,8 +525,8 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
/* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
@@ -500,18 +537,17 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
return retval;
}
-static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr;
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
@@ -527,8 +563,8 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -538,119 +574,119 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
return retval;
}
-static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+static int cortex_a_dpm_finish(struct arm_dpm *dpm)
{
/* REVISIT what could be done here? */
return ERROR_OK;
}
-static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
int retval;
uint32_t dscr = DSCR_INSTR_COMP;
- retval = cortex_a8_write_dcc(a8, data);
+ retval = cortex_a_write_dcc(a, data);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ return cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
}
-static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
- retval = cortex_a8_write_dcc(a8, data);
+ retval = cortex_a_write_dcc(a, data);
if (retval != ERROR_OK)
return retval;
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
/* then the opcode, taking data from R0 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
return retval;
}
-static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
{
struct target *target = dpm->arm->target;
uint32_t dscr = DSCR_INSTR_COMP;
/* "Prefetch flush" after modifying execution status in CPSR */
- return cortex_a8_exec_opcode(target,
+ return cortex_a_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
}
-static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
int retval;
uint32_t dscr = DSCR_INSTR_COMP;
/* the opcode, writing data to DCC */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_read_dcc(a8, data, &dscr);
+ return cortex_a_read_dcc(a, data, &dscr);
}
-static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
/* the opcode, writing data to R0 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_read_dcc(a8, data, &dscr);
+ return cortex_a_read_dcc(a, data, &dscr);
}
-static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t vr = a8->armv7a_common.debug_base;
- uint32_t cr = a8->armv7a_common.debug_base;
+ struct cortex_a_common *a = dpm_to_a(dpm);
+ uint32_t vr = a->armv7a_common.debug_base;
+ uint32_t cr = a->armv7a_common.debug_base;
int retval;
switch (index_t) {
@@ -669,29 +705,29 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
vr += 4 * index_t;
cr += 4 * index_t;
- LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+ LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
- retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
vr, addr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
cr, control);
return retval;
}
-static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t cr;
switch (index_t) {
case 0 ... 15:
- cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE;
break;
case 16 ... 31:
- cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE;
index_t -= 16;
break;
default:
@@ -699,32 +735,32 @@ static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
}
cr += 4 * index_t;
- LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+ LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
/* clear control register */
- return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+ return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
}
-static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
{
- struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+ struct arm_dpm *dpm = &a->armv7a_common.dpm;
int retval;
- dpm->arm = &a8->armv7a_common.arm;
+ dpm->arm = &a->armv7a_common.arm;
dpm->didr = didr;
- dpm->prepare = cortex_a8_dpm_prepare;
- dpm->finish = cortex_a8_dpm_finish;
+ dpm->prepare = cortex_a_dpm_prepare;
+ dpm->finish = cortex_a_dpm_finish;
- dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
- dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
- dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+ dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
+ dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
- dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
- dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+ dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
- dpm->bpwp_enable = cortex_a8_bpwp_enable;
- dpm->bpwp_disable = cortex_a8_bpwp_disable;
+ dpm->bpwp_enable = cortex_a_bpwp_enable;
+ dpm->bpwp_disable = cortex_a_bpwp_disable;
retval = arm_dpm_setup(dpm);
if (retval == ERROR_OK)
@@ -732,7 +768,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
return retval;
}
-static struct target *get_cortex_a8(struct target *target, int32_t coreid)
+static struct target *get_cortex_a(struct target *target, int32_t coreid)
{
struct target_list *head;
struct target *curr;
@@ -746,9 +782,9 @@ static struct target *get_cortex_a8(struct target *target, int32_t coreid)
}
return target;
}
-static int cortex_a8_halt(struct target *target);
+static int cortex_a_halt(struct target *target);
-static int cortex_a8_halt_smp(struct target *target)
+static int cortex_a_halt_smp(struct target *target)
{
int retval = 0;
struct target_list *head;
@@ -756,8 +792,9 @@ static int cortex_a8_halt_smp(struct target *target)
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state != TARGET_HALTED))
- retval += cortex_a8_halt(curr);
+ if ((curr != target) && (curr->state != TARGET_HALTED)
+ && target_was_examined(curr))
+ retval += cortex_a_halt(curr);
head = head->next;
}
return retval;
@@ -766,25 +803,24 @@ static int cortex_a8_halt_smp(struct target *target)
static int update_halt_gdb(struct target *target)
{
int retval = 0;
- if (target->gdb_service->core[0] == -1) {
+ if (target->gdb_service && target->gdb_service->core[0] == -1) {
target->gdb_service->target = target;
target->gdb_service->core[0] = target->coreid;
- retval += cortex_a8_halt_smp(target);
+ retval += cortex_a_halt_smp(target);
}
return retval;
}
/*
- * Cortex-A8 Run control
+ * Cortex-A Run control
*/
-static int cortex_a8_poll(struct target *target)
+static int cortex_a_poll(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct adiv5_dap *swjdp = armv7a->arm.dap;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
enum target_state prev_target_state = target->state;
/* toggle to another core is done by gdb as follow */
/* maint packet J core_id */
@@ -794,15 +830,15 @@ static int cortex_a8_poll(struct target *target)
(target->gdb_service) &&
(target->gdb_service->target == NULL)) {
target->gdb_service->target =
- get_cortex_a8(target, target->gdb_service->core[1]);
+ get_cortex_a(target, target->gdb_service->core[1]);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- cortex_a8->cpudbg_dscr = dscr;
+ cortex_a->cpudbg_dscr = dscr;
if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
if (prev_target_state != TARGET_HALTED) {
@@ -812,7 +848,7 @@ static int cortex_a8_poll(struct target *target)
if ((prev_target_state == TARGET_RUNNING)
|| (prev_target_state == TARGET_UNKNOWN)
|| (prev_target_state == TARGET_RESET)) {
- retval = cortex_a8_debug_entry(target);
+ retval = cortex_a_debug_entry(target);
if (retval != ERROR_OK)
return retval;
if (target->smp) {
@@ -820,13 +856,17 @@ static int cortex_a8_poll(struct target *target)
if (retval != ERROR_OK)
return retval;
}
+
+ if (arm_semihosting(target, &retval) != 0)
+ return retval;
+
target_call_event_callbacks(target,
TARGET_EVENT_HALTED);
}
if (prev_target_state == TARGET_DEBUG_RUNNING) {
LOG_DEBUG(" ");
- retval = cortex_a8_debug_entry(target);
+ retval = cortex_a_debug_entry(target);
if (retval != ERROR_OK)
return retval;
if (target->smp) {
@@ -839,28 +879,23 @@ static int cortex_a8_poll(struct target *target)
TARGET_EVENT_DEBUG_HALTED);
}
}
- } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
+ } else
target->state = TARGET_RUNNING;
- else {
- LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
- target->state = TARGET_UNKNOWN;
- }
return retval;
}
-static int cortex_a8_halt(struct target *target)
+static int cortex_a_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
@@ -868,19 +903,19 @@ static int cortex_a8_halt(struct target *target)
/*
* enter halting debug mode
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@@ -897,8 +932,8 @@ static int cortex_a8_halt(struct target *target)
return ERROR_OK;
}
-static int cortex_a8_internal_restore(struct target *target, int current,
- uint32_t *address, int handle_breakpoints, int debug_execution)
+static int cortex_a_internal_restore(struct target *target, int current,
+ target_addr_t *address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
@@ -953,19 +988,23 @@ static int cortex_a8_internal_restore(struct target *target, int current,
case ARM_STATE_JAZELLE:
LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL;
+ case ARM_STATE_AARCH64:
+ LOG_ERROR("Shoudn't be in AARCH64 state");
+ return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
arm->pc->dirty = 1;
arm->pc->valid = 1;
+
/* restore dpm_mode at system halt */
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
/* called it now before restoring context because it uses cpu
* register r0 for restoring cp15 control register */
- retval = cortex_a8_restore_cp15_control_reg(target);
+ retval = cortex_a_restore_cp15_control_reg(target);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_restore_context(target, handle_breakpoints);
+ retval = cortex_a_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
target->debug_reason = DBG_REASON_NOTHALTED;
@@ -991,11 +1030,10 @@ static int cortex_a8_internal_restore(struct target *target, int current,
return retval;
}
-static int cortex_a8_internal_restart(struct target *target)
+static int cortex_a_internal_restart(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
- struct adiv5_dap *swjdp = arm->dap;
int retval;
uint32_t dscr;
/*
@@ -1006,7 +1044,7 @@ static int cortex_a8_internal_restart(struct target *target)
* disable IRQs by default, with optional override...
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@@ -1014,20 +1052,20 @@ static int cortex_a8_internal_restart(struct target *target)
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@@ -1048,20 +1086,21 @@ static int cortex_a8_internal_restart(struct target *target)
return ERROR_OK;
}
-static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints)
+static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
{
int retval = 0;
struct target_list *head;
struct target *curr;
- uint32_t address;
+ target_addr_t address;
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state != TARGET_RUNNING)) {
+ if ((curr != target) && (curr->state != TARGET_RUNNING)
+ && target_was_examined(curr)) {
/* resume current address , not in step mode */
- retval += cortex_a8_internal_restore(curr, 1, &address,
+ retval += cortex_a_internal_restore(curr, 1, &address,
handle_breakpoints, 0);
- retval += cortex_a8_internal_restart(curr);
+ retval += cortex_a_internal_restart(curr);
}
head = head->next;
@@ -1069,8 +1108,8 @@ static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints)
return retval;
}
-static int cortex_a8_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+static int cortex_a_resume(struct target *target, int current,
+ target_addr_t address, int handle_breakpoints, int debug_execution)
{
int retval = 0;
/* dummy resume for smp toggle in order to reduce gdb impact */
@@ -1082,68 +1121,67 @@ static int cortex_a8_resume(struct target *target, int current,
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
return 0;
}
- cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
+ cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
if (target->smp) {
target->gdb_service->core[0] = -1;
- retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ retval = cortex_a_restore_smp(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
}
- cortex_a8_internal_restart(target);
+ cortex_a_internal_restart(target);
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%" PRIx32, address);
+ LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%" PRIx32, address);
+ LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
}
return ERROR_OK;
}
-static int cortex_a8_debug_entry(struct target *target)
+static int cortex_a_debug_entry(struct target *target)
{
int i;
- uint32_t regfile[16], cpsr, dscr;
+ uint32_t regfile[16], cpsr, spsr, dscr;
int retval = ERROR_OK;
struct working_area *regfile_working_area = NULL;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
- LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
+ LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+ /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
* imprecise data aborts get discarded by issuing a Data
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
/* Examine debug reason */
- arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+ arm_dpm_report_dscr(&armv7a->dpm, cortex_a->cpudbg_dscr);
/* save address of instruction that triggered the watchpoint? */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
@@ -1154,14 +1192,15 @@ static int cortex_a8_debug_entry(struct target *target)
/* REVISIT fast_reg_read is never set ... */
/* Examine target state and mode */
- if (cortex_a8->fast_reg_read)
+ if (cortex_a->fast_reg_read)
target_alloc_working_area(target, 64, ®file_working_area);
+
/* First load register acessible through core debug port*/
if (!regfile_working_area)
retval = arm_dpm_read_current_registers(&armv7a->dpm);
else {
- retval = cortex_a8_read_regs_through_mem(target,
+ retval = cortex_a_read_regs_through_mem(target,
regfile_working_area->address, regfile);
target_free_working_area(target, regfile_working_area);
@@ -1169,7 +1208,7 @@ static int cortex_a8_debug_entry(struct target *target)
return retval;
/* read Current PSR */
- retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ retval = cortex_a_dap_read_coreregister_u32(target, &cpsr, 16);
/* store current cpsr */
if (retval != ERROR_OK)
return retval;
@@ -1201,16 +1240,29 @@ static int cortex_a8_debug_entry(struct target *target)
reg->dirty = reg->valid;
}
+ if (arm->spsr) {
+ /* read Saved PSR */
+ retval = cortex_a_dap_read_coreregister_u32(target, &spsr, 17);
+ /* store current spsr */
+ if (retval != ERROR_OK)
+ return retval;
+
+ reg = arm->spsr;
+ buf_set_u32(reg->value, 0, 32, spsr);
+ reg->valid = 1;
+ reg->dirty = 0;
+ }
+
#if 0
/* TODO, Move this */
uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
- cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
+ cortex_a_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
- cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
+ cortex_a_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
- cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
+ cortex_a_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
#endif
@@ -1225,43 +1277,76 @@ static int cortex_a8_debug_entry(struct target *target)
return retval;
}
-static int cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a_post_debug_entry(struct target *target)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
int retval;
/* MRC p15,0,