X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=13b8ca54930c753603cf7d8c9ed21f0e9ea7f468;hb=bd0fbef5c8819c9f58b48f02acd862d9be4d87b9;hp=9b8ba41665fb4a517ec9c8c9854f8d697f20ce81;hpb=5578935eff66ed6db4a8f6b6957ab671dd36732b;p=fw%2Fopenocd
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
old mode 100755
new mode 100644
index 9b8ba4166..13b8ca549
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -17,6 +17,9 @@
* Copyright (C) ST-Ericsson SA 2011 *
* michel.jaouen@stericsson.com : smp minimum support *
* *
+ * Copyright (C) Broadcom 2012 *
+ * ehunter@broadcom.com : Cortex R4 support *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -30,12 +33,14 @@
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
* *
* Cortex-A8(tm) TRM, ARM DDI 0344H *
* Cortex-A9(tm) TRM, ARM DDI 0407F *
+ * Cortex-A4(tm) TRM, ARM DDI 0363E *
* *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -52,31 +57,108 @@ static int cortex_a8_poll(struct target *target);
static int cortex_a8_debug_entry(struct target *target);
static int cortex_a8_restore_context(struct target *target, bool bpwp);
static int cortex_a8_set_breakpoint(struct target *target,
- struct breakpoint *breakpoint, uint8_t matchmode);
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_set_context_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_set_hybrid_breakpoint(struct target *target,
+ struct breakpoint *breakpoint);
static int cortex_a8_unset_breakpoint(struct target *target,
- struct breakpoint *breakpoint);
+ struct breakpoint *breakpoint);
static int cortex_a8_dap_read_coreregister_u32(struct target *target,
- uint32_t *value, int regnum);
+ uint32_t *value, int regnum);
static int cortex_a8_dap_write_coreregister_u32(struct target *target,
- uint32_t value, int regnum);
+ uint32_t value, int regnum);
static int cortex_a8_mmu(struct target *target, int *enabled);
static int cortex_a8_virt2phys(struct target *target,
- uint32_t virt, uint32_t *phys);
-static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
+ uint32_t virt, uint32_t *phys);
+static int cortex_a8_read_apb_ab_memory(struct target *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-/*
- * FIXME do topology discovery using the ROM; don't
- * assume this is an OMAP3. Also, allow for multiple ARMv7-A
- * cores, with different AP numbering ... don't use a #define
- * for these numbers, use per-core armv7a state.
- */
-#define swjdp_memoryap 0
-#define swjdp_debugap 1
+/* restore cp15_control_reg at resume */
+static int cortex_a8_restore_cp15_control_reg(struct target *target)
+{
+ int retval = ERROR_OK;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+
+ if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) {
+ cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
+ /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg);
+ }
+ return retval;
+}
+
+/* check address before cortex_a8_apb read write access with mmu on
+ * remove apb predictible data abort */
+static int cortex_a8_check_address(struct target *target, uint32_t address)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ uint32_t os_border = armv7a->armv7a_mmu.os_border;
+ if ((address < os_border) &&
+ (armv7a->arm.core_mode == ARM_MODE_SVC)) {
+ LOG_ERROR("%" PRIx32 " access in userspace and target in supervisor", address);
+ return ERROR_FAIL;
+ }
+ if ((address >= os_border) &&
+ (cortex_a8->curr_mode != ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+ cortex_a8->curr_mode = ARM_MODE_SVC;
+ LOG_INFO("%" PRIx32 " access in kernel space and target not in supervisor",
+ address);
+ return ERROR_OK;
+ }
+ if ((address < os_border) &&
+ (cortex_a8->curr_mode == ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ cortex_a8->curr_mode = ARM_MODE_ANY;
+ }
+ return ERROR_OK;
+}
+/* modify cp15_control_reg in order to enable or disable mmu for :
+ * - virt2phys address conversion
+ * - read or write memory in phys or virt address */
+static int cortex_a8_mmu_modify(struct target *target, int enable)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ int retval = ERROR_OK;
+ if (enable) {
+ /* if mmu enabled at target stop and mmu not enable */
+ if (!(cortex_a8->cp15_control_reg & 0x1U)) {
+ LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
+ return ERROR_FAIL;
+ }
+ if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) {
+ cortex_a8->cp15_control_reg_curr |= 0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ } else {
+ if (cortex_a8->cp15_control_reg_curr & 0x4U) {
+ /* data cache is active */
+ cortex_a8->cp15_control_reg_curr &= ~0x4U;
+ /* flush data cache armv7 function to be called */
+ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
+ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
+ }
+ if ((cortex_a8->cp15_control_reg_curr & 0x1U)) {
+ cortex_a8->cp15_control_reg_curr &= ~0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ }
+ return retval;
+}
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
@@ -84,32 +166,30 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
uint32_t dummy;
LOG_DEBUG(" ");
- /* Unlocking the debug registers for modification */
- /* The debugport might be uninitialised so try twice */
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ /* Unlocking the debug registers for modification
+ * The debugport might be uninitialised so try twice */
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
- if (retval != ERROR_OK)
- {
+ if (retval != ERROR_OK) {
/* try again */
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval == ERROR_OK)
- {
- LOG_USER("Locking debug access failed on first, but succeeded on second try.");
- }
+ LOG_USER(
+ "Locking debug access failed on first, but succeeded on second try.");
}
if (retval != ERROR_OK)
return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_PRSR, &dummy);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_PRSR, &dummy);
if (retval != ERROR_OK)
return retval;
@@ -127,12 +207,12 @@ static int cortex_a8_init_debug_access(struct target *target)
* happen to know that no instruction is pending.
*/
static int cortex_a8_exec_opcode(struct target *target,
- uint32_t opcode, uint32_t *dscr_p)
+ uint32_t opcode, uint32_t *dscr_p)
{
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
@@ -140,44 +220,37 @@ static int cortex_a8_exec_opcode(struct target *target,
/* Wait for InstrCompl bit to be set */
long long then = timeval_ms();
- while ((dscr & DSCR_INSTR_COMP) == 0)
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ while ((dscr & DSCR_INSTR_COMP) == 0) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
return retval;
}
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
return ERROR_FAIL;
}
}
- retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_ITR, opcode);
+ retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
then = timeval_ms();
- do
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ do {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
return retval;
}
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
return ERROR_FAIL;
}
- }
- while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
+ } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
if (dscr_p)
*dscr_p = dscr;
@@ -190,11 +263,11 @@ Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
- uint32_t * regfile)
+ uint32_t *regfile)
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
@@ -206,35 +279,32 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
- (uint8_t *)(®file[1]), 4*15, address);
+ retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap,
+ (uint8_t *)(®file[1]), 4, 15, address);
return retval;
}
static int cortex_a8_dap_read_coreregister_u32(struct target *target,
- uint32_t *value, int regnum)
+ uint32_t *value, int regnum)
{
int retval = ERROR_OK;
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
- if (reg < 15)
- {
+ if (reg < 15) {
/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- }
- else if (reg == 15)
- {
+ } else if (reg == 15) {
/* "MOV r0, r15"; then move r0 to DCCTX */
retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
if (retval != ERROR_OK)
@@ -244,9 +314,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
&dscr);
if (retval != ERROR_OK)
return retval;
- }
- else
- {
+ } else {
/* "MRS r0, CPSR" or "MRS r0, SPSR"
* then move r0 to DCCTX
*/
@@ -262,20 +330,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
/* Wait for DTRRXfull then read DTRRTX */
long long then = timeval_ms();
- while ((dscr & DSCR_DTR_TX_FULL) == 0)
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ while ((dscr & DSCR_DTR_TX_FULL) == 0) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
return ERROR_FAIL;
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
@@ -283,23 +349,22 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
}
static int cortex_a8_dap_write_coreregister_u32(struct target *target,
- uint32_t value, int regnum)
+ uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if (dscr & DSCR_DTR_RX_FULL)
- {
+ if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
@@ -313,22 +378,19 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
- retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
- if (Rd < 15)
- {
+ if (Rd < 15) {
/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
-
+
if (retval != ERROR_OK)
return retval;
- }
- else if (Rd == 15)
- {
+ } else if (Rd == 15) {
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0"
*/
@@ -339,9 +401,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
if (retval != ERROR_OK)
return retval;
- }
- else
- {
+ } else {
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
@@ -355,8 +415,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
- if (Rd == 16)
- {
+ if (Rd == 16) {
retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
@@ -369,13 +428,15 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target,
+ uint32_t address,
+ uint32_t value)
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, address, value);
return retval;
}
@@ -399,14 +460,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(a8->armv7a_common.armv4_5_common.dap,
- swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+ return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap,
+ a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
- uint32_t *dscr_p)
+ uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
@@ -416,23 +477,22 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
/* Wait for DTRRXfull */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for read dcc");
return ERROR_FAIL;
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
- //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+ /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
if (dscr_p)
*dscr_p = dscr;
@@ -443,23 +503,21 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
long long then = timeval_ms();
- for (;;)
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ for (;; ) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
if ((dscr & DSCR_INSTR_COMP) != 0)
break;
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for dpm prepare");
return ERROR_FAIL;
}
@@ -470,7 +528,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -487,7 +545,7 @@ static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
}
static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
- uint32_t opcode, uint32_t data)
+ uint32_t opcode, uint32_t data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
@@ -498,13 +556,13 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
return retval;
return cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
}
static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
- uint32_t opcode, uint32_t data)
+ uint32_t opcode, uint32_t data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
@@ -516,7 +574,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -524,7 +582,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
/* then the opcode, taking data from R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
@@ -543,7 +601,7 @@ static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
}
static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
- uint32_t opcode, uint32_t *data)
+ uint32_t opcode, uint32_t *data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
@@ -551,7 +609,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
/* the opcode, writing data to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
@@ -562,7 +620,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
- uint32_t opcode, uint32_t *data)
+ uint32_t opcode, uint32_t *data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
@@ -570,7 +628,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
/* the opcode, writing data to R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
@@ -578,7 +636,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
/* write R0 to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
@@ -588,7 +646,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
}
static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
- uint32_t addr, uint32_t control)
+ uint32_t addr, uint32_t control)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
uint32_t vr = a8->armv7a_common.debug_base;
@@ -596,23 +654,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
int retval;
switch (index_t) {
- case 0 ... 15: /* breakpoints */
- vr += CPUDBG_BVR_BASE;
- cr += CPUDBG_BCR_BASE;
- break;
- case 16 ... 31: /* watchpoints */
- vr += CPUDBG_WVR_BASE;
- cr += CPUDBG_WCR_BASE;
- index_t -= 16;
- break;
- default:
- return ERROR_FAIL;
+ case 0 ... 15: /* breakpoints */
+ vr += CPUDBG_BVR_BASE;
+ cr += CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31: /* watchpoints */
+ vr += CPUDBG_WVR_BASE;
+ cr += CPUDBG_WCR_BASE;
+ index_t -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
}
vr += 4 * index_t;
cr += 4 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
- (unsigned) vr, (unsigned) cr);
+ (unsigned) vr, (unsigned) cr);
retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
vr, addr);
@@ -629,15 +687,15 @@ static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
uint32_t cr;
switch (index_t) {
- case 0 ... 15:
- cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
- break;
- case 16 ... 31:
- cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
- index_t -= 16;
- break;
- default:
- return ERROR_FAIL;
+ case 0 ... 15:
+ cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31:
+ cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ index_t -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
}
cr += 4 * index_t;
@@ -652,7 +710,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
struct arm_dpm *dpm = &a8->armv7a_common.dpm;
int retval;
- dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->arm = &a8->armv7a_common.arm;
dpm->didr = didr;
dpm->prepare = cortex_a8_dpm_prepare;
@@ -676,20 +734,17 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
}
static struct target *get_cortex_a8(struct target *target, int32_t coreid)
{
-struct target_list *head;
-struct target *curr;
+ struct target_list *head;
+ struct target *curr;
head = target->head;
- while(head != (struct target_list*)NULL)
- {
+ while (head != (struct target_list *)NULL) {
curr = head->target;
if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
- {
- return curr;
- }
+ return curr;
head = head->next;
}
- return target;
+ return target;
}
static int cortex_a8_halt(struct target *target);
@@ -699,13 +754,10 @@ static int cortex_a8_halt_smp(struct target *target)
struct target_list *head;
struct target *curr;
head = target->head;
- while(head != (struct target_list*)NULL)
- {
+ while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state!= TARGET_HALTED))
- {
+ if ((curr != target) && (curr->state != TARGET_HALTED))
retval += cortex_a8_halt(curr);
- }
head = head->next;
}
return retval;
@@ -714,8 +766,7 @@ static int cortex_a8_halt_smp(struct target *target)
static int update_halt_gdb(struct target *target)
{
int retval = 0;
- if (target->gdb_service->core[0]==-1)
- {
+ if (target->gdb_service->core[0] == -1) {
target->gdb_service->target = target;
target->gdb_service->core[0] = target->coreid;
retval += cortex_a8_halt_smp(target);
@@ -733,77 +784,64 @@ static int cortex_a8_poll(struct target *target)
uint32_t dscr;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
- // toggle to another core is done by gdb as follow
- // maint packet J core_id
- // continue
- // the next polling trigger an halt event sent to gdb
+ /* toggle to another core is done by gdb as follow */
+ /* maint packet J core_id */
+ /* continue */
+ /* the next polling trigger an halt event sent to gdb */
if ((target->state == TARGET_HALTED) && (target->smp) &&
- (target->gdb_service) &&
- (target->gdb_service->target==NULL) )
- {
+ (target->gdb_service) &&
+ (target->gdb_service->target == NULL)) {
target->gdb_service->target =
get_cortex_a8(target, target->gdb_service->core[1]);
- target_call_event_callbacks(target,
- TARGET_EVENT_HALTED);
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
- {
return retval;
- }
cortex_a8->cpudbg_dscr = dscr;
- if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
- {
- if (prev_target_state != TARGET_HALTED)
- {
+ if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
+ if (prev_target_state != TARGET_HALTED) {
/* We have a halting debug event */
LOG_DEBUG("Target halted");
target->state = TARGET_HALTED;
if ((prev_target_state == TARGET_RUNNING)
- || (prev_target_state == TARGET_RESET))
- {
+ || (prev_target_state == TARGET_UNKNOWN)
+ || (prev_target_state == TARGET_RESET)) {
retval = cortex_a8_debug_entry(target);
if (retval != ERROR_OK)
return retval;
- if (target->smp)
- {
+ if (target->smp) {
retval = update_halt_gdb(target);
if (retval != ERROR_OK)
return retval;
}
target_call_event_callbacks(target,
- TARGET_EVENT_HALTED);
+ TARGET_EVENT_HALTED);
}
- if (prev_target_state == TARGET_DEBUG_RUNNING)
- {
+ if (prev_target_state == TARGET_DEBUG_RUNNING) {
LOG_DEBUG(" ");
retval = cortex_a8_debug_entry(target);
if (retval != ERROR_OK)
return retval;
- if (target->smp)
- {
+ if (target->smp) {
retval = update_halt_gdb(target);
if (retval != ERROR_OK)
return retval;
}
target_call_event_callbacks(target,
- TARGET_EVENT_DEBUG_HALTED);
+ TARGET_EVENT_DEBUG_HALTED);
}
}
- }
- else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
- {
+ } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
target->state = TARGET_RUNNING;
- }
- else
- {
+ else {
LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
target->state = TARGET_UNKNOWN;
}
@@ -816,13 +854,13 @@ static int cortex_a8_halt(struct target *target)
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
@@ -830,29 +868,25 @@ static int cortex_a8_halt(struct target *target)
/*
* enter halting debug mode
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
- for (;;)
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ for (;; ) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if ((dscr & DSCR_CORE_HALTED) != 0)
- {
break;
- }
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for halt");
return ERROR_FAIL;
}
@@ -864,10 +898,10 @@ static int cortex_a8_halt(struct target *target)
}
static int cortex_a8_internal_restore(struct target *target, int current,
- uint32_t *address, int handle_breakpoints, int debug_execution)
+ uint32_t *address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *arm = &armv7a->arm;
int retval;
uint32_t resume_pc;
@@ -875,8 +909,7 @@ static int cortex_a8_internal_restore(struct target *target, int current,
target_free_all_working_areas(target);
#if 0
- if (debug_execution)
- {
+ if (debug_execution) {
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of
* masking with C_MASKINTS,
@@ -889,14 +922,15 @@ static int cortex_a8_internal_restore(struct target *target, int current,
/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
+ 32) | (1 << 24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
#endif
/* current = 1: continue on current pc, otherwise continue at
*/
- resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
+ resume_pc = buf_get_u32(arm->pc->value, 0, 32);
if (!current)
resume_pc = *address;
else
@@ -905,43 +939,47 @@ static int cortex_a8_internal_restore(struct target *target, int current,
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- switch (armv4_5->core_state)
- {
- case ARM_STATE_ARM:
- resume_pc &= 0xFFFFFFFC;
- break;
- case ARM_STATE_THUMB:
- case ARM_STATE_THUMB_EE:
- /* When the return address is loaded into PC
- * bit 0 must be 1 to stay in Thumb state
- */
- resume_pc |= 0x1;
- break;
- case ARM_STATE_JAZELLE:
- LOG_ERROR("How do I resume into Jazelle state??");
- return ERROR_FAIL;
+ switch (arm->core_state) {
+ case ARM_STATE_ARM:
+ resume_pc &= 0xFFFFFFFC;
+ break;
+ case ARM_STATE_THUMB:
+ case ARM_STATE_THUMB_EE:
+ /* When the return address is loaded into PC
+ * bit 0 must be 1 to stay in Thumb state
+ */
+ resume_pc |= 0x1;
+ break;
+ case ARM_STATE_JAZELLE:
+ LOG_ERROR("How do I resume into Jazelle state??");
+ return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
- armv4_5->pc->dirty = 1;
- armv4_5->pc->valid = 1;
-
+ buf_set_u32(arm->pc->value, 0, 32, resume_pc);
+ arm->pc->dirty = 1;
+ arm->pc->valid = 1;
+ /* restore dpm_mode at system halt */
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ /* called it now before restoring context because it uses cpu
+ * register r0 for restoring cp15 control register */
+ retval = cortex_a8_restore_cp15_control_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
retval = cortex_a8_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
- target->debug_reason = DBG_REASON_NOTHALTED;
+ target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
/* registers are now invalid */
- register_cache_invalidate(armv4_5->core_cache);
+ register_cache_invalidate(arm->core_cache);
#if 0
/* the front-end may request us not to handle breakpoints */
- if (handle_breakpoints)
- {
+ if (handle_breakpoints) {
/* Single step past breakpoint at current address */
- if ((breakpoint = breakpoint_find(target, resume_pc)))
- {
+ breakpoint = breakpoint_find(target, resume_pc);
+ if (breakpoint) {
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
cortex_m3_unset_breakpoint(target, breakpoint);
cortex_m3_single_step_core(target);
@@ -956,19 +994,19 @@ static int cortex_a8_internal_restore(struct target *target, int current,
static int cortex_a8_internal_restart(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = armv4_5->dap;
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = arm->dap;
int retval;
uint32_t dscr;
-/*
- * Restart core and wait for it to be started. Clear ITRen and sticky
- * exception flags: see ARMv7 ARM, C5.9.
+ /*
+ * * Restart core and wait for it to be started. Clear ITRen and sticky
+ * * exception flags: see ARMv7 ARM, C5.9.
*
* REVISIT: for single stepping, we probably want to
* disable IRQs by default, with optional override...
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@@ -976,28 +1014,26 @@ static int cortex_a8_internal_restart(struct target *target)
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
- for (;;)
- {
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ for (;; ) {
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if ((dscr & DSCR_CORE_RESTARTED) != 0)
break;
- if (timeval_ms() > then + 1000)
- {
+ if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for resume");
return ERROR_FAIL;
}
@@ -1007,27 +1043,25 @@ static int cortex_a8_internal_restart(struct target *target)
target->state = TARGET_RUNNING;
/* registers are now invalid */
- register_cache_invalidate(armv4_5->core_cache);
+ register_cache_invalidate(arm->core_cache);
return ERROR_OK;
}
-static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints)
+static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints)
{
int retval = 0;
struct target_list *head;
struct target *curr;
- uint32_t address;
+ uint32_t address;
head = target->head;
- while(head != (struct target_list*)NULL)
- {
+ while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state != TARGET_RUNNING))
- {
- /* resume current address , not in step mode */
- retval += cortex_a8_internal_restore(curr, 1, &address,
- handle_breakpoints, 0);
- retval += cortex_a8_internal_restart(curr);
+ if ((curr != target) && (curr->state != TARGET_RUNNING)) {
+ /* resume current address , not in step mode */
+ retval += cortex_a8_internal_restore(curr, 1, &address,
+ handle_breakpoints, 0);
+ retval += cortex_a8_internal_restart(curr);
}
head = head->next;
@@ -1036,12 +1070,11 @@ static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints)
}
static int cortex_a8_resume(struct target *target, int current,
- uint32_t address, int handle_breakpoints, int debug_execution)
+ uint32_t address, int handle_breakpoints, int debug_execution)
{
int retval = 0;
- /* dummy resume for smp toggle in order to reduce gdb impact */
- if ((target->smp) && (target->gdb_service->core[1]!=-1))
- {
+ /* dummy resume for smp toggle in order to reduce gdb impact */
+ if ((target->smp) && (target->gdb_service->core[1] != -1)) {
/* simulate a start and halt of target */
target->gdb_service->target = NULL;
target->gdb_service->core[0] = target->gdb_service->core[1];
@@ -1050,20 +1083,19 @@ static int cortex_a8_resume(struct target *target, int current,
return 0;
}
cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
- if (target->smp)
- { target->gdb_service->core[0] = -1;
- retval += cortex_a8_restore_smp(target, handle_breakpoints);
+ if (target->smp) {
+ target->gdb_service->core[0] = -1;
+ retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
}
cortex_a8_internal_restart(target);
- if (!debug_execution)
- {
+ if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32, address);
- }
- else
- {
+ } else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, address);
@@ -1080,15 +1112,15 @@ static int cortex_a8_debug_entry(struct target *target)
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@@ -1099,7 +1131,7 @@ static int cortex_a8_debug_entry(struct target *target)
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
- retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
@@ -1111,7 +1143,7 @@ static int cortex_a8_debug_entry(struct target *target)
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
- retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
@@ -1127,33 +1159,28 @@ static int cortex_a8_debug_entry(struct target *target)
/* First load register acessible through core debug port*/
if (!regfile_working_area)
- {
retval = arm_dpm_read_current_registers(&armv7a->dpm);
- }
- else
- {
+ else {
retval = cortex_a8_read_regs_through_mem(target,
regfile_working_area->address, regfile);
target_free_working_area(target, regfile_working_area);
if (retval != ERROR_OK)
- {
return retval;
- }
/* read Current PSR */
retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ /* store current cpsr */
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- arm_set_cpsr(armv4_5, cpsr);
+ arm_set_cpsr(arm, cpsr);
/* update cache */
- for (i = 0; i <= ARM_PC; i++)
- {
- reg = arm_reg_current(armv4_5, i);
+ for (i = 0; i <= ARM_PC; i++) {
+ reg = arm_reg_current(arm, i);
buf_set_u32(reg->value, 0, 32, regfile[i]);
reg->valid = 1;
@@ -1161,18 +1188,15 @@ static int cortex_a8_debug_entry(struct target *target)
}
/* Fixup PC Resume Address */
- if (cpsr & (1 << 5))
- {
- // T bit set for Thumb or ThumbEE state
+ if (cpsr & (1 << 5)) {
+ /* T bit set for Thumb or ThumbEE state */
regfile[ARM_PC] -= 4;
- }
- else
- {
- // ARM state
+ } else {
+ /* ARM state */
regfile[ARM_PC] -= 8;
}
- reg = armv4_5->pc;
+ reg = arm->pc;
buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
reg->dirty = reg->valid;
}
@@ -1191,9 +1215,8 @@ static int cortex_a8_debug_entry(struct target *target)
#endif
/* Are we in an exception handler */
-// armv4_5->exception_number = 0;
- if (armv7a->post_debug_entry)
- {
+/* armv4_5->exception_number = 0; */
+ if (armv7a->post_debug_entry) {
retval = armv7a->post_debug_entry(target);
if (retval != ERROR_OK)
return retval;
@@ -1209,68 +1232,54 @@ static int cortex_a8_post_debug_entry(struct target *target)
int retval;
/* MRC p15,0,