X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farmv8_cache.c;h=86e4a59615451a1bdf6821cef7ee301bb33d760c;hb=28c24a5c41c47a66e9310912f88148814f730a25;hp=31e4c79600ce412b39ddddd68bb5db7ff121ad50;hpb=62c2eb4b284e0a3deb2aad7163354200bd93e634;p=fw%2Fopenocd

diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index 31e4c7960..86e4a5961 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -49,8 +49,9 @@ static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
 	return ERROR_TARGET_INVALID;
 }
 
-static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
+static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
 {
+	struct arm_dpm *dpm = armv8->arm.dpm;
 	int retval = ERROR_OK;
 	int32_t c_way, c_index = size->index;
 
@@ -65,7 +66,7 @@ static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cac
 			 * line by Set/Way.
 			 */
 			retval = dpm->instr_write_data_r0(dpm,
-					ARMV8_SYS(SYSTEM_DCCISW, 0), value);
+					armv8_opcode(armv8, ARMV8_OPC_DCCISW), value);
 			if (retval != ERROR_OK)
 				goto done;
 			c_way -= 1;
@@ -97,7 +98,7 @@ static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
 		if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
 			continue;
 
-		armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
+		armv8_cache_d_inner_flush_level(armv8, &cache->arch[cl].d_u_size, cl);
 	}
 
 	retval = dpm->finish(dpm);
@@ -133,7 +134,7 @@ int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va,
 		/* DC CIVAC */
 		/* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
 		retval = dpm->instr_write_data_r0_64(dpm,
-				ARMV8_SYS(SYSTEM_DCCIVAC, 0), va_line);
+				armv8_opcode(armv8, ARMV8_OPC_DCCIVAC), va_line);
 		if (retval != ERROR_OK)
 			goto done;
 		va_line += linelen;
@@ -171,7 +172,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
 	while (va_line < va_end) {
 		/* IC IVAU - Invalidate instruction cache by VA to PoU. */
 		retval = dpm->instr_write_data_r0_64(dpm,
-				ARMV8_SYS(SYSTEM_ICIVAU, 0), va_line);
+				armv8_opcode(armv8, ARMV8_OPC_ICIVAU), va_line);
 		if (retval != ERROR_OK)
 			goto done;
 		va_line += linelen;
@@ -187,13 +188,13 @@ done:
 	return retval;
 }
 
-static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
+static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
 	struct armv8_cache_common *armv8_cache)
 {
 	int cl;
 
 	if (armv8_cache->info == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
@@ -201,11 +202,11 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
 		struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
 
 		if (arch->ctype & 1) {
-			command_print(cmd_ctx,
-				"L%d I-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+			command_print(cmd,
+				"L%d I-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->i_size.linelen,
 				arch->i_size.associativity,
@@ -214,11 +215,11 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
 		}
 
 		if (arch->ctype >= 2) {
-			command_print(cmd_ctx,
-				"L%d D-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+			command_print(cmd,
+				"L%d D-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->d_u_size.linelen,
 				arch->d_u_size.associativity,
@@ -309,6 +310,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 {
 	/*  read cache descriptor */
 	int retval = ERROR_FAIL;
+	struct arm *arm = &armv8->arm;
 	struct arm_dpm *dpm = armv8->arm.dpm;
 	uint32_t csselr, clidr, ctr;
 	uint32_t cache_reg;
@@ -319,6 +321,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
 	if (retval != ERROR_OK)
 		goto done;
 
+	/* check if we're in an unprivileged mode */
+	if (armv8_curel_from_core_mode(arm->core_mode) < SYSTEM_CUREL_EL1) {
+		retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+		if (retval != ERROR_OK)
+			return retval;
+	}
+
 	/* retrieve CTR */
 	retval = dpm->instr_read_data_r0(dpm,
 			armv8_opcode(armv8, READ_REG_CTR), &ctr);
@@ -327,7 +336,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 
 	cache->iminline = 4UL << (ctr & 0xf);
 	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR */
@@ -364,13 +373,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
 				goto done;
 			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+			LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].d_u_size.index,
 					cache->arch[cl].d_u_size.index_shift,
 					cache->arch[cl].d_u_size.way,
 					cache->arch[cl].d_u_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].d_u_size.linelen,
 					cache->arch[cl].d_u_size.cachesize,
 					cache->arch[cl].d_u_size.associativity);
@@ -384,13 +393,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
 				goto done;
 			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+			LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].i_size.index,
 					cache->arch[cl].i_size.index_shift,
 					cache->arch[cl].i_size.way,
 					cache->arch[cl].i_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].i_size.linelen,
 					cache->arch[cl].i_size.cachesize,
 					cache->arch[cl].i_size.associativity);
@@ -416,6 +425,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 	}
 
 done:
+	armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
 	dpm->finish(dpm);
 	return retval;