X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.c;h=170cfcc28db2dbee92f7361b6efb0135486a8908;hb=571db89aa13554d5c5e38e88233927d3149edc3a;hp=e95e99b07b32cf1e655166137bc0fc41fbdbccfa;hpb=f97a1594119f90f63526e1fa8a95dbcba0acd192;p=fw%2Fopenocd diff --git a/src/target/armv7a.c b/src/target/armv7a.c index e95e99b07..170cfcc28 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -16,7 +16,7 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -88,11 +88,50 @@ done: /* (void) */ dpm->finish(dpm); } + +/* retrieve main id register */ +static int armv7a_read_midr(struct target *target) +{ + int retval = ERROR_FAIL; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm_dpm *dpm = armv7a->arm.dpm; + uint32_t midr; + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + /* MRC p15,0,,c0,c0,0; read main id register*/ + + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 0, 0, 0), + &midr); + if (retval != ERROR_OK) + goto done; + + armv7a->rev = (midr & 0xf); + armv7a->partnum = (midr >> 4) & 0xfff; + armv7a->arch = (midr >> 16) & 0xf; + armv7a->variant = (midr >> 20) & 0xf; + armv7a->implementor = (midr >> 24) & 0xff; + LOG_INFO("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32 + ", variant %" PRIx32 ", implementor %" PRIx32, + target->cmd_name, + armv7a->rev, + armv7a->partnum, + armv7a->arch, + armv7a->variant, + armv7a->implementor); + +done: + dpm->finish(dpm); + return retval; +} + static int armv7a_read_ttbcr(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t ttbcr; + uint32_t ttbr0, ttbr1; int retval = dpm->prepare(dpm); if (retval != ERROR_OK) goto done; @@ -102,27 +141,55 @@ static int armv7a_read_ttbcr(struct target *target) &ttbcr); if (retval != ERROR_OK) goto done; + + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 2, 0, 0), + &ttbr0); + if (retval != ERROR_OK) + goto done; + + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 2, 0, 1), + &ttbr1); + if (retval != ERROR_OK) + goto done; + + LOG_INFO("ttbcr %" PRIx32 "ttbr0 %" PRIx32 "ttbr1 %" PRIx32, ttbcr, ttbr0, ttbr1); + armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0; - armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7))); -#if 0 - LOG_INFO("ttb1 %s ,ttb0_mask %x", - armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used", - armv7a->armv7a_mmu.ttbr0_mask); -#endif - if (armv7a->armv7a_mmu.ttbr1_used == 1) { - LOG_INFO("SVC access above %x", - (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); - armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask; + armv7a->armv7a_mmu.ttbr0_mask = 0; + + retval = armv7a_read_midr(target); + if (retval != ERROR_OK) + goto done; + + if (armv7a->partnum & 0xf) { + /* + * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition), + * document # ARM DDI 0406C + */ + armv7a->armv7a_mmu.ttbr0_mask = 1 << (14 - ((ttbcr & 0x7))); } else { + /* ARM DDI 0344H , ARM DDI 0407F */ + armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7))); /* fix me , default is hard coded LINUX border */ armv7a->armv7a_mmu.os_border = 0xc0000000; } + + LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32, + armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used", + armv7a->armv7a_mmu.ttbr0_mask); + + if (armv7a->armv7a_mmu.ttbr1_used == 1) { + LOG_INFO("SVC access above %" PRIx32, + (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); + armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask; + } done: dpm->finish(dpm); return retval; } - /* method adapted to cortex A : reused arm v4 v5 method*/ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) { @@ -165,27 +232,26 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) } - if ((first_lvl_descriptor & 0x3) == 2) { + if ((first_lvl_descriptor & 0x40002) == 2) { /* section descriptor */ *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff); return ERROR_OK; + } else if ((first_lvl_descriptor & 0x40002) == 0x40002) { + /* supersection descriptor */ + if (first_lvl_descriptor & 0x00f001e0) { + LOG_ERROR("Physical address does not fit into 32 bits"); + return ERROR_TARGET_TRANSLATION_FAULT; + } + *val = (first_lvl_descriptor & 0xff000000) | (va & 0x00ffffff); + return ERROR_OK; } - if ((first_lvl_descriptor & 0x3) == 1) { - /* coarse page table */ - retval = armv7a->armv7a_mmu.read_physical_memory(target, - (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), - 4, 1, (uint8_t *)&second_lvl_descriptor); - if (retval != ERROR_OK) - return retval; - } else if ((first_lvl_descriptor & 0x3) == 3) { - /* fine page table */ - retval = armv7a->armv7a_mmu.read_physical_memory(target, - (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), - 4, 1, (uint8_t *)&second_lvl_descriptor); - if (retval != ERROR_OK) - return retval; - } + /* page table */ + retval = armv7a->armv7a_mmu.read_physical_memory(target, + (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), + 4, 1, (uint8_t *)&second_lvl_descriptor); + if (retval != ERROR_OK) + return retval; second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *) &second_lvl_descriptor); @@ -200,23 +266,12 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) if ((second_lvl_descriptor & 0x3) == 1) { /* large page descriptor */ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff); - return ERROR_OK; - } - - if ((second_lvl_descriptor & 0x3) == 2) { + } else { /* small page descriptor */ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff); - return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 3) { - *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff); - return ERROR_OK; - } - - /* should not happen */ - LOG_ERROR("Address translation failure"); - return ERROR_TARGET_TRANSLATION_FAULT; + return ERROR_OK; done: return retval; @@ -257,7 +312,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, if (*val == va) LOG_WARNING("virt = phys : MMU disable !!"); if (meminfo) { - LOG_INFO("%x : %x %s outer shareable %s secured", + LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured", va, *val, NOS == 1 ? "not" : " ", NS == 1 ? "not" : ""); @@ -295,7 +350,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, LOG_INFO("inner: Write-Back, no Write-Allocate"); default: - LOG_INFO("inner: %x ???", INNER); + LOG_INFO("inner: %" PRIx32 " ???", INNER); } } @@ -314,14 +369,14 @@ static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ct } command_print(cmd_ctx, - "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->d_u_size.linelen, armv7a_cache->d_u_size.associativity, armv7a_cache->d_u_size.nsets, armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->i_size.linelen, armv7a_cache->i_size.associativity, armv7a_cache->i_size.nsets, @@ -388,7 +443,7 @@ static int armv7a_flush_all_data(struct target *target) while (head != (struct target_list *)NULL) { curr = head->target; if (curr->state == TARGET_HALTED) { - LOG_INFO("Wait flushing data l1 on core %d", curr->coreid); + LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid); retval = _armv7a_flush_all_data(curr); } head = head->next; @@ -434,19 +489,19 @@ static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx, } command_print(cmd_ctx, - "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->d_u_size.linelen, armv7a_cache->d_u_size.associativity, armv7a_cache->d_u_size.nsets, armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->i_size.linelen, armv7a_cache->i_size.associativity, armv7a_cache->i_size.nsets, armv7a_cache->i_size.cachesize); - command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways", + command_print(cmd_ctx, "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways", l2x_cache->base, l2x_cache->way); @@ -468,7 +523,7 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t l2x_cache->base,l2x_cache->way);*/ if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) LOG_INFO("cache l2 already initialized\n"); - armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache; + armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache; /* initialize l1 / l2x cache function */ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = armv7a_l2x_flush_all_data; @@ -482,7 +537,7 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t armv7a = target_to_armv7a(curr); if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) LOG_ERROR("smp target : cache l2 already initialized\n"); - armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache; + armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = armv7a_l2x_flush_all_data; armv7a->armv7a_mmu.armv7a_cache.display_cache_info = @@ -497,21 +552,17 @@ COMMAND_HANDLER(handle_cache_l2x) { struct target *target = get_current_target(CMD_CTX); uint32_t base, way; - switch (CMD_ARGC) { - case 0: - return ERROR_COMMAND_SYNTAX_ERROR; - break; - case 2: - /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */ - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way); - - /* AP address is in bits 31:24 of DP_SELECT */ - armv7a_l2x_cache_init(target, base, way); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } + + if (CMD_ARGC != 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */ + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way); + + /* AP address is in bits 31:24 of DP_SELECT */ + armv7a_l2x_cache_init(target, base, way); + return ERROR_OK; } @@ -545,17 +596,27 @@ static int armv7a_read_mpidr(struct target *target) &mpidr); if (retval != ERROR_OK) goto done; + + /* ARMv7R uses a different format for MPIDR. + * When configured uniprocessor (most R cores) it reads as 0. + * This will need to be implemented for multiprocessor ARMv7R cores. */ + if (armv7a->is_armv7r) { + if (mpidr) + LOG_ERROR("MPIDR nonzero in ARMv7-R target"); + goto done; + } + if (mpidr & 1<<31) { armv7a->multi_processor_system = (mpidr >> 30) & 1; armv7a->cluster_id = (mpidr >> 8) & 0xf; armv7a->cpu_id = mpidr & 0x3; - LOG_INFO("%s cluster %x core %x %s", target->cmd_name, + LOG_INFO("%s cluster %x core %x %s", target_name(target), armv7a->cluster_id, armv7a->cpu_id, armv7a->multi_processor_system == 0 ? "multi core" : "mono core"); } else - LOG_ERROR("mpdir not in multiprocessor format"); + LOG_ERROR("MPIDR not in multiprocessor format"); done: dpm->finish(dpm); @@ -573,7 +634,8 @@ int armv7a_identify_cache(struct target *target) uint32_t cache_selected, clidr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); - armv7a_read_ttbcr(target); + if (!armv7a->is_armv7r) + armv7a_read_ttbcr(target); retval = dpm->prepare(dpm); if (retval != ERROR_OK) @@ -586,7 +648,7 @@ int armv7a_identify_cache(struct target *target) if (retval != ERROR_OK) goto done; clidr = (clidr & 0x7000000) >> 23; - LOG_INFO("number of cache level %d", clidr / 2); + LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2)); if ((clidr / 2) > 1) { /* FIXME not supported present in cortex A8 and later */ /* in cortex A7, A15 */ @@ -747,10 +809,16 @@ int armv7a_arch_state(struct target *target) arm_arch_state(target); - LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", - state[armv7a->armv7a_mmu.mmu_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + if (armv7a->is_armv7r) { + LOG_USER("D-Cache: %s, I-Cache: %s", + state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + } else { + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", + state[armv7a->armv7a_mmu.mmu_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + } if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); @@ -778,7 +846,7 @@ const struct command_registration l2x_cache_command_handlers[] = { { .name = "cache_config", .mode = COMMAND_EXEC, - .help = "cache configuation for a target", + .help = "cache configuration for a target", .usage = "", .chain = l2_cache_commands, },