X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=c087b772678dbd774c6612fa25974cf32daa8dae;hb=ad800b1c0224141a6dcebd0b0573417c44a495dd;hp=4ed0558605e17bd5cc030dc608413012848a1711;hpb=13eac429e1b2b6b9061a58c05dc7e67415d5ad0e;p=fw%2Fopenocd diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 4ed055860..c087b7726 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -2,6 +2,9 @@ * Copyright (C) 2006 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2008 by Hongtao Zheng * + * hontor@126.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -21,20 +24,18 @@ #include "config.h" #endif -#include "target.h" #include "armv4_5.h" #include "arm_disassembler.h" #include "arm_simulator.h" #include "log.h" #include "binarybuffer.h" -#include -u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry) +uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *carry) { - u32 return_value; + uint32_t return_value = 0; shift_amount &= 0xff; - + if (shift == 0x0) /* LSL */ { if ((shift_amount > 0) && (shift_amount <= 32)) @@ -117,57 +118,57 @@ u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry) Rm |= 0x80000000; *carry = Rm & 0x1; } - + return return_value; } -u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, u8 *shifter_carry_out) +uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out) { - u32 return_value; + uint32_t return_value; int instruction_size; - + if (armv4_5->core_state == ARMV4_5_STATE_ARM) instruction_size = 4; else instruction_size = 2; - + *shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1); - + if (variant == 0) /* 32-bit immediate */ { return_value = shifter_operand.immediate.immediate; } else if (variant == 1) /* immediate shift */ { - u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32); - + uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32); + /* adjust RM in case the PC is being read */ if (shifter_operand.immediate_shift.Rm == 15) Rm += 2 * instruction_size; - + return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out); } else if (variant == 2) /* register shift */ { - u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32); - u32 Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32); - + uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32); + uint32_t Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32); + /* adjust RM in case the PC is being read */ if (shifter_operand.register_shift.Rm == 15) Rm += 2 * instruction_size; - + return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out); } else { - ERROR("BUG: shifter_operand.variant not 0, 1 or 2"); + LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2"); return_value = 0xffffffff; } - + return return_value; } -int pass_condition(u32 cpsr, u32 opcode) +int pass_condition(uint32_t cpsr, uint32_t opcode) { switch ((opcode & 0xf0000000) >> 28) { @@ -250,38 +251,45 @@ int pass_condition(u32 cpsr, u32 opcode) case 0xe: case 0xf: return 1; - + } - - ERROR("BUG: should never get here"); + + LOG_ERROR("BUG: should never get here"); return 0; } -int thumb_pass_branch_condition(u32 cpsr, u16 opcode) +int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode) { - return pass_condition(cpsr, (opcode & 0x0f00) << 20); + return pass_condition(cpsr, (opcode & 0x0f00) << 20); } /* simulate a single step (if possible) * if the dry_run_pc argument is provided, no state is changed, * but the new pc is stored in the variable pointed at by the argument */ -int arm_simulate_step(target_t *target, u32 *dry_run_pc) +int arm_simulate_step(target_t *target, uint32_t *dry_run_pc) { armv4_5_common_t *armv4_5 = target->arch_info; - u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + uint32_t current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); arm_instruction_t instruction; int instruction_size; - + int retval = ERROR_OK; + if (armv4_5->core_state == ARMV4_5_STATE_ARM) { - u32 opcode; - + uint32_t opcode; + /* get current instruction, and identify it */ - target_read_u32(target, current_pc, &opcode); - arm_evaluate_opcode(opcode, current_pc, &instruction); + if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK) + { + return retval; + } + if ((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK) + { + return retval; + } instruction_size = 4; - + /* check condition code (for all instructions) */ if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) { @@ -293,18 +301,24 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) { buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size); } - + return ERROR_OK; } } else { - u16 opcode; - - target_read_u16(target, current_pc, &opcode); - thumb_evaluate_opcode(opcode, current_pc, &instruction); + uint16_t opcode; + + if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK) + { + return retval; + } + if ((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK) + { + return retval; + } instruction_size = 2; - + /* check condition code (only for branch instructions) */ if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) && (instruction.type == ARM_B)) @@ -317,29 +331,33 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) { buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size); } - + return ERROR_OK; } } - + /* examine instruction type */ /* branch instructions */ if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX)) { - u32 target; - + uint32_t target; + if (instruction.info.b_bl_bx_blx.reg_operand == -1) { target = instruction.info.b_bl_bx_blx.target_address; } else { - target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32); + target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32); + if (instruction.info.b_bl_bx_blx.reg_operand == 15) + { + target += 2 * instruction_size; + } } - + if (dry_run_pc) - { + { *dry_run_pc = target; return ERROR_OK; } @@ -351,7 +369,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else if (instruction.type == ARM_BL) { - u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + uint32_t old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4); buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target); } @@ -369,7 +387,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else if (instruction.type == ARM_BLX) { - u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + uint32_t old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4); if (target & 0x1) @@ -382,7 +400,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe); } - + return ERROR_OK; } } @@ -390,18 +408,23 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC)) || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) { - u32 Rd, Rn, shifter_operand; - u8 C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1); - u8 carry_out; - + uint32_t Rd, Rn, shifter_operand; + uint8_t C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1); + uint8_t carry_out; + Rd = 0x0; - Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32); + /* ARM_MOV and ARM_MVN does not use Rn */ + if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN)) + Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32); + else + Rn = 0; + shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out); /* adjust Rn in case the PC is being read */ if (instruction.info.data_proc.Rn == 15) Rn += 2 * instruction_size; - + if (instruction.type == ARM_AND) Rd = Rn & shifter_operand; else if (instruction.type == ARM_EOR) @@ -426,7 +449,9 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) Rd = shifter_operand; else if (instruction.type == ARM_MVN) Rd = ~shifter_operand; - + else + LOG_WARNING("unhandled instruction type"); + if (dry_run_pc) { if (instruction.info.data_proc.Rd == 15) @@ -438,15 +463,15 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) { *dry_run_pc = current_pc + instruction_size; } - + return ERROR_OK; } else { buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd); - WARNING("no updating of flags yet"); + LOG_WARNING("no updating of flags yet"); - if (instruction.info.data_proc.Rd == 15) + if (instruction.info.data_proc.Rd == 15) return ERROR_OK; } } @@ -460,19 +485,19 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else { - WARNING("no updating of flags yet"); + LOG_WARNING("no updating of flags yet"); } } /* load register instructions */ else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { - u32 load_address, modified_address, load_value; - u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32); - + uint32_t load_address = 0, modified_address = 0, load_value; + uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32); + /* adjust Rn in case the PC is being read */ if (instruction.info.load_store.Rn == 15) Rn += 2 * instruction_size; - + if (instruction.info.load_store.offset_mode == 0) { if (instruction.info.load_store.U) @@ -482,14 +507,14 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else if (instruction.info.load_store.offset_mode == 1) { - u32 offset; - u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32); - u8 shift = instruction.info.load_store.offset.reg.shift; - u8 shift_imm = instruction.info.load_store.offset.reg.shift_imm; - u8 carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1); - + uint32_t offset; + uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32); + uint8_t shift = instruction.info.load_store.offset.reg.shift; + uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm; + uint8_t carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1); + offset = arm_shift(shift, Rm, shift_imm, &carry); - + if (instruction.info.load_store.U) modified_address = Rn + offset; else @@ -497,9 +522,9 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else { - ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)"); + LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)"); } - + if (instruction.info.load_store.index_mode == 0) { /* offset mode @@ -519,9 +544,15 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) * we load from the unmodified address, and write the modified address back */ load_address = Rn; } - - target_read_u32(target, load_address, &load_value); - + + if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) + { + if ((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK) + { + return retval; + } + } + if (dry_run_pc) { if (instruction.info.load_store.Rd == 15) @@ -533,7 +564,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) { *dry_run_pc = current_pc + instruction_size; } - + return ERROR_OK; } else @@ -542,9 +573,9 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) (instruction.info.load_store.index_mode == 2)) { buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32, modified_address); - } + } buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rd).value, 0, 32, load_value); - + if (instruction.info.load_store.Rd == 15) return ERROR_OK; } @@ -553,8 +584,8 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) else if (instruction.type == ARM_LDM) { int i; - u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32); - u32 load_values[16]; + uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32); + uint32_t load_values[16]; int bits_set = 0; for (i = 0; i < 16; i++) @@ -562,7 +593,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) if (instruction.info.load_store_multiple.register_list & (1 << i)) bits_set++; } - + switch (instruction.info.load_store_multiple.addressing_mode) { case 0: /* Increment after */ @@ -572,7 +603,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) Rn = Rn + 4; break; case 2: /* Decrement after */ - Rn = Rn - (bits_set * 4) + 4; + Rn = Rn - (bits_set * 4) + 4; break; case 3: /* Decrement before */ Rn = Rn - (bits_set * 4); @@ -583,11 +614,14 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) { if (instruction.info.load_store_multiple.register_list & (1 << i)) { - target_read_u32(target, Rn, &load_values[i]); + if ((!dry_run_pc) || (i == 15)) + { + target_read_u32(target, Rn, &load_values[i]); + } Rn += 4; } } - + if (dry_run_pc) { if (instruction.info.load_store_multiple.register_list & 0x8000) @@ -616,17 +650,17 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, i).value, 0, 32, load_values[i]); } } - + if (update_cpsr) { - u32 spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32); + uint32_t spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32); buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr); } - + /* base register writeback */ if (instruction.info.load_store_multiple.W) - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); - + buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); + if (instruction.info.load_store_multiple.register_list & 0x8000) return ERROR_OK; } @@ -642,7 +676,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else { - u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32); + uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32); int bits_set = 0; enum armv4_5_mode mode = armv4_5->core_mode; @@ -651,12 +685,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) if (instruction.info.load_store_multiple.register_list & (1 << i)) bits_set++; } - + if (instruction.info.load_store_multiple.S) { mode = ARMV4_5_MODE_USR; } - + switch (instruction.info.load_store_multiple.addressing_mode) { case 0: /* Increment after */ @@ -666,13 +700,13 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) Rn = Rn + 4; break; case 2: /* Decrement after */ - Rn = Rn - (bits_set * 4) + 4; + Rn = Rn - (bits_set * 4) + 4; break; case 3: /* Decrement before */ Rn = Rn - (bits_set * 4); break; } - + for (i = 0; i < 16; i++) { if (instruction.info.load_store_multiple.register_list & (1 << i)) @@ -681,11 +715,11 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) Rn += 4; } } - + /* base register writeback */ if (instruction.info.load_store_multiple.W) - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); - + buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn); + } } else if (!dry_run_pc) @@ -694,7 +728,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) */ return ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED; } - + if (dry_run_pc) { *dry_run_pc = current_pc + instruction_size; @@ -705,5 +739,5 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size); return ERROR_OK; } - + }