X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm_opcodes.h;h=9a48e6d03acdde0fb906de6c44f2c5185d099512;hb=54d6330b78f46678e78d1ffb265c65fcc8991e83;hp=58498ac26feee640bbf9dbd03d8e58c023f264d3;hpb=910dd664ceb6faef5e9029e9b0848d7ccc63bf4b;p=fw%2Fopenocd

diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
old mode 100644
new mode 100755
index 58498ac26..9a48e6d03
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -2,6 +2,9 @@
  * Copyright (C) 2005 by Dominic Rath
  * Dominic.Rath@gmx.de
  *
+ * Copyright (C) 2006 by Magnus Lundin
+ * lundin@mlu.mine.nu
+ *
  * Copyright (C) 2008 by Spencer Oliver
  * spen@spen-soft.co.uk
  *
@@ -83,6 +86,12 @@
 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
 	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 
+/* Load Register Word Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRW_IP(Rd, Rn)	(0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) 
+	
 /* Load Register Halfword Immediate Post-Index
  * Rd: register to load
  * Rn: base register
@@ -95,6 +104,12 @@
  */
 #define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 
+/* Store register Word Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRW_IP(Rd, Rn)	(0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) 
+
 /* Store register Halfword Immediate Post-Index
  * Rd: register to store
  * Rn: base register