X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=7d914bfd38710cbbd24fc37a6c07f0dd861ddf4c;hb=9eb3181cc8bb0b82d6c9e580c2042274e5490b77;hp=df84ba0f59e28cf6870ff2cfff8598418da6ed64;hpb=b9628accd6da0aef6a9fc03efb96e05afab99c99;p=fw%2Fopenocd

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index df84ba0f5..7d914bfd3 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -120,18 +120,83 @@ enum arm_instruction_type
 	ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
+typedef struct arm_b_bl_bx_blx_instr_s
+{
+	int reg_operand;
+	uint32_t target_address;
+} arm_b_bl_bx_blx_instr_t;
+
+union arm_shifter_operand
+{
+	struct {
+		uint32_t immediate;
+	} immediate;
+	struct {
+		uint8_t Rm;
+		uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+		uint8_t shift_imm;
+	} immediate_shift;
+	struct {
+		uint8_t Rm;
+		uint8_t shift;
+		uint8_t Rs;
+	} register_shift;
+};
+
+typedef struct arm_data_proc_instr_s
+{
+	int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
+	uint8_t S;
+	uint8_t Rn;
+	uint8_t Rd;
+	union arm_shifter_operand shifter_operand;
+} arm_data_proc_instr_t;
+
+typedef struct arm_load_store_instr_s
+{
+	uint8_t Rd;
+	uint8_t Rn;
+	uint8_t U;
+	int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
+	int offset_mode; /* 0: immediate, 1: (scaled) register */
+	union
+	{
+		uint32_t offset;
+		struct {
+			uint8_t Rm;
+			uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
+			uint8_t shift_imm;
+		} reg;
+	} offset;
+} arm_load_store_instr_t;
+
+typedef struct arm_load_store_multiple_instr_s
+{
+	uint8_t Rn;
+	uint32_t register_list;
+	uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
+	uint8_t S;
+	uint8_t W;
+} arm_load_store_multiple_instr_t;
+
 typedef struct arm_instruction_s
 {
 	enum arm_instruction_type type;
 	char text[128];
-	u32 opcode;
-	
-	/* target */
-	u32 target_address;
-	
+	uint32_t opcode;
+	
+	union {
+		arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
+		arm_data_proc_instr_t data_proc;
+		arm_load_store_instr_t load_store;
+		arm_load_store_multiple_instr_t load_store_multiple;
+	} info;
+
 } arm_instruction_t;
 
-extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
+extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
+extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
+extern int arm_access_size(arm_instruction_t *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])