X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=1be567475c402b8b477c8073e4872184eb8b139d;hb=HEAD;hp=c6dc6967d809daca2dbb70dd3e66aec22f50476b;hpb=1f76f6999974a3a1765aaa96fecc3f2433e7b5b6;p=fw%2Fopenocd diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index c6dc6967d..1be567475 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -1,37 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2006 by Dominic Rath * * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -#ifndef ARM_DISASSEMBLER_H -#define ARM_DISASSEMBLER_H -#include "types.h" +#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H +#define OPENOCD_TARGET_ARM_DISASSEMBLER_H + +enum arm_instruction_type { + ARM_UNKNOWN_INSTRUCTION, -enum arm_instruction_type -{ - ARM_UNKNOWN_INSTUCTION, - /* Branch instructions */ ARM_B, ARM_BL, ARM_BX, ARM_BLX, - + /* Data processing instructions */ ARM_AND, ARM_EOR, @@ -49,32 +34,32 @@ enum arm_instruction_type ARM_MOV, ARM_BIC, ARM_MVN, - + /* Load/store instructions */ ARM_LDR, ARM_LDRB, ARM_LDRT, ARM_LDRBT, - + ARM_LDRH, ARM_LDRSB, ARM_LDRSH, - + ARM_LDM, ARM_STR, ARM_STRB, ARM_STRT, ARM_STRBT, - + ARM_STRH, - + ARM_STM, - + /* Status register access instructions */ ARM_MRS, ARM_MSR, - + /* Multiply instructions */ ARM_MUL, ARM_MLA, @@ -82,118 +67,131 @@ enum arm_instruction_type ARM_SMLAL, ARM_UMULL, ARM_UMLAL, - + /* Miscellaneous instructions */ ARM_CLZ, - + + /* Exception return instructions */ + ARM_ERET, + /* Exception generating instructions */ ARM_BKPT, ARM_SWI, - + ARM_HVC, + ARM_SMC, + /* Coprocessor instructions */ ARM_CDP, ARM_LDC, ARM_STC, ARM_MCR, ARM_MRC, - + /* Semaphore instructions */ ARM_SWP, ARM_SWPB, - + /* Enhanced DSP extensions */ ARM_MCRR, ARM_MRRC, ARM_PLD, + ARM_DSB, + ARM_ISB, ARM_QADD, ARM_QDADD, ARM_QSUB, ARM_QDSUB, - ARM_SMLAxy, - ARM_SMLALxy, - ARM_SMLAWy, - ARM_SMULxy, - ARM_SMULWy, + ARM_SMLAXY, + ARM_SMLALXY, + ARM_SMLAWY, + ARM_SMULXY, + ARM_SMULWY, ARM_LDRD, ARM_STRD, ARM_UNDEFINED_INSTRUCTION = 0xffffffff, }; -typedef struct arm_b_bl_bx_blx_instr_s -{ +struct arm_b_bl_bx_blx_instr { int reg_operand; - u32 target_address; -} arm_b_bl_bx_blx_instr_t; + uint32_t target_address; +}; + +union arm_shifter_operand { + struct { + uint32_t immediate; + } immediate; + struct { + uint8_t rm; + uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ + uint8_t shift_imm; + } immediate_shift; + struct { + uint8_t rm; + uint8_t shift; + uint8_t rs; + } register_shift; +}; -typedef struct arm_data_proc_instr_s -{ +struct arm_data_proc_instr { int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */ - u8 S; - u8 Rn; - u8 Rd; - union - { - struct { - u8 immediate; - } immediate; - struct { - u8 Rm; - u8 shift; - u8 shift_imm; - } immediate_shift; - struct { - u8 Rm; - u8 shift; - u8 Rs; - } register_shift; - } shifter_operand; -} arm_data_proc_instr_t; - -typedef struct arm_load_store_instr_s -{ - u8 Rd; - u8 Rn; - u8 U; + uint8_t s; + uint8_t rn; + uint8_t rd; + union arm_shifter_operand shifter_operand; +}; + +struct arm_load_store_instr { + uint8_t rd; + uint8_t rn; + uint8_t u; int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */ int offset_mode; /* 0: immediate, 1: (scaled) register */ - union - { - u32 offset; + union { + uint32_t offset; struct { - u8 Rm; - u8 shift; - u8 shift_imm; + uint8_t rm; + uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ + uint8_t shift_imm; } reg; } offset; -} arm_load_store_instr_t; - -typedef struct arm_load_store_multiple_instr_s -{ - u8 Rn; - u32 register_list; - u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ - u8 S; - u8 W; -} arm_load_store_multiple_instr_t; - -typedef struct arm_instruction_s -{ +}; + +struct arm_load_store_multiple_instr { + uint8_t rn; + uint32_t register_list; + uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ + uint8_t s; + uint8_t w; +}; + +struct arm_instruction { enum arm_instruction_type type; char text[128]; - u32 opcode; - + uint32_t opcode; + + /* return value ... Thumb-2 sizes vary */ + unsigned instruction_size; + union { - arm_b_bl_bx_blx_instr_t b_bl_bx_blx; - arm_data_proc_instr_t data_proc; - arm_load_store_instr_t load_store; - arm_load_store_multiple_instr_t load_store_multiple; + struct arm_b_bl_bx_blx_instr b_bl_bx_blx; + struct arm_data_proc_instr data_proc; + struct arm_load_store_instr load_store; + struct arm_load_store_multiple_instr load_store_multiple; } info; -} arm_instruction_t; +}; -extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction); +int arm_evaluate_opcode(uint32_t opcode, uint32_t address, + struct arm_instruction *instruction); +int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, + struct arm_instruction *instruction); +int arm_access_size(struct arm_instruction *instruction); +#if HAVE_CAPSTONE +int arm_disassemble(struct command_invocation *cmd, struct target *target, + target_addr_t address, size_t count, bool thumb_mode); +#endif -#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28]) +#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28]) -#endif /* ARM_DISASSEMBLER_H */ +#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */