X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=f46760e54e07b16c843b98fb32b765090e6805c7;hb=f1e72cf029f28a337679ca787003c54d5c1e2bde;hp=87603bca89a514aa28d2a6365b2ca9c41bda0d4a;hpb=bc67c6720b246652bc0915b1b6d036ada6c85fda;p=fw%2Fopenocd diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 87603bca8..f46760e54 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -72,7 +72,6 @@ target_type_t arm926ejs_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - .prepare_reset_halt = arm7_9_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, @@ -91,6 +90,7 @@ target_type_t arm926ejs_target = .register_commands = arm926ejs_register_commands, .target_command = arm926ejs_target_command, .init_target = arm926ejs_init_target, + .examine = arm9tdmi_examine, .quit = arm926ejs_quit, .virt2phys = arm926ejs_virt2phys, .mmu = arm926ejs_mmu @@ -108,7 +108,7 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field) } else if ((t == 0x0f) || (t == 0x00)) { - DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access"); + LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access"); return ERROR_OK; } return ERROR_JTAG_QUEUE_FAILED;; @@ -178,6 +178,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[0].in_handler_priv = value; fields[0].in_handler = arm_jtag_buf_to_u32; + /*TODO: add timeout*/ do { /* rescan with NOP, to wait for the access to complete */ @@ -188,7 +189,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 } while (buf_get_u32(&access, 0, 1) != 1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - DEBUG("addr: 0x%x value: %8.8x", address, *value); + LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); #endif arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan); @@ -256,7 +257,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[3].in_handler_priv = NULL; jtag_add_dr_scan(4, fields, -1); - + /*TODO: add timeout*/ do { /* rescan with NOP, to wait for the access to complete */ @@ -267,7 +268,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u } while (buf_get_u32(&access, 0, 1) != 1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - DEBUG("addr: 0x%x value: %8.8x", address, value); + LOG_DEBUG("addr: 0x%x value: %8.8x", address, value); #endif arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan); @@ -292,54 +293,56 @@ int arm926ejs_examine_debug_reason(target_t *target) switch (debug_reason) { case 1: - DEBUG("breakpoint from EICE unit 0"); + LOG_DEBUG("breakpoint from EICE unit 0"); target->debug_reason = DBG_REASON_BREAKPOINT; break; case 2: - DEBUG("breakpoint from EICE unit 1"); + LOG_DEBUG("breakpoint from EICE unit 1"); target->debug_reason = DBG_REASON_BREAKPOINT; break; case 3: - DEBUG("soft breakpoint (BKPT instruction)"); + LOG_DEBUG("soft breakpoint (BKPT instruction)"); target->debug_reason = DBG_REASON_BREAKPOINT; break; case 4: - DEBUG("vector catch breakpoint"); + LOG_DEBUG("vector catch breakpoint"); target->debug_reason = DBG_REASON_BREAKPOINT; break; case 5: - DEBUG("external breakpoint"); + LOG_DEBUG("external breakpoint"); target->debug_reason = DBG_REASON_BREAKPOINT; break; case 6: - DEBUG("watchpoint from EICE unit 0"); + LOG_DEBUG("watchpoint from EICE unit 0"); target->debug_reason = DBG_REASON_WATCHPOINT; break; case 7: - DEBUG("watchpoint from EICE unit 1"); + LOG_DEBUG("watchpoint from EICE unit 1"); target->debug_reason = DBG_REASON_WATCHPOINT; break; case 8: - DEBUG("external watchpoint"); + LOG_DEBUG("external watchpoint"); target->debug_reason = DBG_REASON_WATCHPOINT; break; case 9: - DEBUG("internal debug request"); + LOG_DEBUG("internal debug request"); target->debug_reason = DBG_REASON_DBGRQ; break; case 10: - DEBUG("external debug request"); + LOG_DEBUG("external debug request"); target->debug_reason = DBG_REASON_DBGRQ; break; case 11: - ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); + LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); break; default: - ERROR("BUG: unknown debug reason: 0x%x", debug_reason); + LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); target->debug_reason = DBG_REASON_DBGRQ; + retval = ERROR_TARGET_FAILURE; + break; } - return ERROR_OK; + return retval; } u32 arm926ejs_get_ttb(target_t *target) @@ -442,7 +445,7 @@ void arm926ejs_post_debug_entry(target_t *target) /* examine cp15 control reg */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); jtag_execute_queue(); - DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) { @@ -462,7 +465,7 @@ void arm926ejs_post_debug_entry(target_t *target) arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); - DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", + LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); @@ -548,11 +551,11 @@ int arm926ejs_arch_state(struct target_s *target) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - USER( + LOG_USER( "target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s", @@ -575,16 +578,27 @@ int arm926ejs_soft_reset_halt(struct target_s *target) arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + int i; + + target_halt(target); - if (target->state == TARGET_RUNNING) + for (i=0; i<10; i++) { - target->type->halt(target); + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + { + embeddedice_read_reg(dbg_stat); + jtag_execute_queue(); + } else + { + break; + } + /* do not eat all CPU, time out after 1 se*/ + usleep(100*1000); } - - while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + if (i==10) { - embeddedice_read_reg(dbg_stat); - jtag_execute_queue(); + LOG_ERROR("Failed to halt CPU after 1 sec"); + return ERROR_TARGET_TIMEOUT; } target->state = TARGET_HALTED; @@ -706,7 +720,7 @@ int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char if (argc < 4) { - ERROR("'target arm926ejs' requires at least one additional argument"); + LOG_ERROR("'target arm926ejs' requires at least one additional argument"); exit(-1); } @@ -715,7 +729,7 @@ int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char if (argc >= 5) variant = args[4]; - DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); + LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant); @@ -937,7 +951,7 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled) if (target->state != TARGET_HALTED) { - ERROR("Target not halted"); + LOG_ERROR("Target not halted"); return ERROR_TARGET_INVALID; } *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;