X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=0d6f0172d9d0c57aef70ce9a9e5bf890c6a0a183;hb=84df52f9ea78e2d71bde648a16b69d80404c6421;hp=26e7f19fe8f9a44588922f9520b801ba91f5b82b;hpb=db7e77237c5a8104b527aeb23a2546b4bab92d8a;p=fw%2Fopenocd

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 26e7f19fe..0d6f0172d 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -167,7 +167,7 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
 		nr_w_buf = 0;
 		jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-		jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
+		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
@@ -317,7 +317,7 @@ int arm926ejs_examine_debug_reason(target_t *target)
 			 * openocd development mailing list if you have hardware
 			 * to donate to look into this problem....
 			 */
-			LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
+			LOG_ERROR("mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
 			target->debug_reason = DBG_REASON_DBGRQ;
 			retval = ERROR_TARGET_FAILURE;
 			break;
@@ -433,7 +433,7 @@ void arm926ejs_post_debug_entry(target_t *target)
 	/* examine cp15 control reg */
 	arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
 	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
@@ -453,7 +453,7 @@ void arm926ejs_post_debug_entry(target_t *target)
 	arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 	arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 
-	LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
 	uint32_t cache_dbg_ctrl;
@@ -544,7 +544,7 @@ int arm926ejs_arch_state(struct target_s *target)
 
 	LOG_USER(
 			"target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8x pc: 0x%8.8x\n"
+			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
@@ -572,9 +572,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 		return retval;
 	}
 
-	long long then=timeval_ms();
+	long long then = timeval_ms();
 	int timeout;
-	while (!(timeout=((timeval_ms()-then)>1000)))
+	while (!(timeout = ((timeval_ms()-then)>1000)))
 	{
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
@@ -587,7 +587,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 		{
 			break;
 		}
-		if (debug_level>=1)
+		if (debug_level >= 1)
 		{
 			/* do not eat all CPU, time out after 1 se*/
 			alive_sleep(100);
@@ -789,7 +789,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
 			return retval;
 		}
 
-		command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+		command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
 	}
 	else
 	{
@@ -799,7 +799,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
 			command_print(cmd_ctx, "couldn't access register");
 			return ERROR_OK;
 		}
-		command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+		command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
 	}
 
 	return ERROR_OK;