X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=6287891bb3437a336e88b222fd804ba1a6340d81;hb=ed028542edef963acfea6b67a07ba2dd396543de;hp=3bbe8b07ad27c30fac93152e2ef8b31f8d446d2c;hpb=3e71449adec41bf2a9f498d027aae0ba6e83721f;p=fw%2Fopenocd

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3bbe8b07a..6287891bb 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -392,6 +392,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
 			{
 				return retval;
 			}
+			current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 			if (current_instr == arm7_9->thumb_bkpt)
 				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 				{
@@ -1518,7 +1519,10 @@ static int arm7_9_full_context(struct target *target)
 	}
 
 	if (!is_arm_mode(armv4_5->core_mode))
+	{
+		LOG_ERROR("not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
+	}
 
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
 	 * SYS shares registers with User, so we don't touch SYS
@@ -1621,7 +1625,10 @@ static int arm7_9_restore_context(struct target *target)
 		arm7_9->pre_restore_context(target);
 
 	if (!is_arm_mode(armv4_5->core_mode))
+	{
+		LOG_ERROR("not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
+	}
 
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
 	 * SYS shares registers with User, so we don't touch SYS
@@ -2425,7 +2432,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 	return ERROR_OK;
 }
 
-int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct arm *armv4_5 = &arm7_9->armv4_5_common;
@@ -2649,7 +2656,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 }
 
 static int dcc_count;
-static uint8_t *dcc_buffer;
+static const uint8_t *dcc_buffer;
 
 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
@@ -2661,7 +2668,7 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int
 
 	int little = target->endianness == TARGET_LITTLE_ENDIAN;
 	int count = dcc_count;
-	uint8_t *buffer = dcc_buffer;
+	const uint8_t *buffer = dcc_buffer;
 	if (count > 2)
 	{
 		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
@@ -2714,7 +2721,7 @@ static const uint32_t dcc_code[] =
 	0xeafffff9	/*    b   w                   */
 };
 
-int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
 {
 	int retval;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);