X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=3fe8efa95ee11f0b9d857f224cfb4b5be0aba2ea;hb=597ec356e3ac04ce231fc18bf873e3000c50693a;hp=cd4eba1ad8a1c1a45205a28dd34807a57c279a40;hpb=c497006430ed270e047bf2e911165f7c826600ed;p=fw%2Fopenocd diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index cd4eba1ad..3fe8efa95 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -8,6 +8,9 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * + * Copyright (C) 2008 by Hongtao Zheng * + * hontor@126.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -39,6 +42,7 @@ #include "arm7_9_common.h" #include "breakpoints.h" #include "time_support.h" +#include "arm_simulator.h" #include #include @@ -62,7 +66,6 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -75,6 +78,26 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) return jtag_execute_queue(); } +static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) +{ + if (!arm7_9->wp0_used) + { + arm7_9->wp0_used = 1; + breakpoint->set = 1; + arm7_9->wp_available--; + } + else if (!arm7_9->wp1_used) + { + arm7_9->wp1_used = 1; + breakpoint->set = 2; + arm7_9->wp_available--; + } + else + { + LOG_ERROR("BUG: no hardware comparator available"); + } +} + /* set up embedded ice registers */ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) { @@ -139,7 +162,6 @@ int arm7_9_setup(target_t *target) return arm7_9_clear_watchpoints(arm7_9); } - int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -180,6 +202,13 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */ u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u; + + /* reassign a hw breakpoint */ + if (breakpoint->set==0) + { + arm7_9_assign_wp(arm7_9, breakpoint); + } + if (breakpoint->set==1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); @@ -217,11 +246,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u32 verify = 0xffffffff; /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt); + if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK) + { + return retval; + } - target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify); + if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK) + { + return retval; + } if (verify != arm7_9->arm_bkpt) { LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); @@ -232,11 +270,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u16 verify = 0xffff; /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */ - target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt); + if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK) + { + return retval; + } - target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify); + if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK) + { + return retval; + } if (verify != arm7_9->thumb_bkpt) { LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); @@ -247,11 +294,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } return retval; - } int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval = ERROR_OK; + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -267,13 +315,15 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); arm7_9->wp0_used = 0; + arm7_9->wp_available++; } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->wp1_used = 0; + arm7_9->wp_available++; } - jtag_execute_queue(); + retval = jtag_execute_queue(); breakpoint->set = 0; } else @@ -283,22 +333,34 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u32 current_instr; /* check that user program as not modified breakpoint instruction */ - target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK) + { + return retval; + } if (current_instr==arm7_9->arm_bkpt) - target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { u16 current_instr; /* check that user program as not modified breakpoint instruction */ - target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK) + { + return retval; + } if (current_instr==arm7_9->thumb_bkpt) - target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } breakpoint->set = 0; } - return ERROR_OK; + return retval; } int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) @@ -334,25 +396,9 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { - arm7_9->wp_available--; - - if (!arm7_9->wp0_used) - { - arm7_9->wp0_used = 1; - breakpoint->set = 1; - } - else if (!arm7_9->wp1_used) - { - arm7_9->wp1_used = 1; - breakpoint->set = 2; - } - else - { - LOG_ERROR("BUG: no hardware comparator available"); - } + arm7_9_assign_wp(arm7_9, breakpoint); } - arm7_9->breakpoint_count++; return arm7_9_set_breakpoint(target, breakpoint); @@ -360,10 +406,14 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7_9_unset_breakpoint(target, breakpoint); + if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } if (breakpoint->type == BKPT_HARD) arm7_9->wp_available++; @@ -372,7 +422,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (arm7_9->breakpoint_count==0) { /* make sure we don't have any dangling breakpoints */ - arm7_9_clear_watchpoints(arm7_9); + if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) + { + return retval; + } } return ERROR_OK; @@ -380,6 +433,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; int rw_mask = 1; @@ -408,7 +462,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } watchpoint->set = 1; arm7_9->wp0_used = 2; } @@ -422,7 +479,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } watchpoint->set = 2; arm7_9->wp1_used = 2; } @@ -437,6 +497,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -455,13 +516,19 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (watchpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } arm7_9->wp0_used = 0; } else if (watchpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } arm7_9->wp1_used = 0; } watchpoint->set = 0; @@ -497,12 +564,16 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; if (watchpoint->set) { - arm7_9_unset_watchpoint(target, watchpoint); + if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK) + { + return retval; + } } arm7_9->wp_available++; @@ -510,9 +581,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } - - - int arm7_9_execute_sys_speed(struct target_s *target) { int retval; @@ -523,7 +591,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -569,7 +637,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -581,9 +649,9 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) /* check for DBGACK and SYSCOMP set (others don't care) */ /* NB! These are constants that must be available until after next jtag_execute() and - we evaluate the values upon first execution in lieu of setting up these constants - during early setup. - */ + * we evaluate the values upon first execution in lieu of setting up these constants + * during early setup. + * */ buf_set_u32(check_value, 0, 32, 0x9); buf_set_u32(check_mask, 0, 32, 0x9); set=1; @@ -601,11 +669,12 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; u32 *data; - int i; + int retval = ERROR_OK; + u32 i; data = malloc(size * (sizeof(u32))); - embeddedice_receive(jtag_info, data, size); + retval = embeddedice_receive(jtag_info, data, size); for (i = 0; i < size; i++) { @@ -614,11 +683,12 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) free(data); - return ERROR_OK; + return retval; } int arm7_9_handle_target_request(void *priv) { + int retval = ERROR_OK; target_t *target = priv; if (!target->type->examined) return ERROR_OK; @@ -627,7 +697,6 @@ int arm7_9_handle_target_request(void *priv) arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; - if (!target->dbg_msg_enabled) return ERROR_OK; @@ -635,15 +704,24 @@ int arm7_9_handle_target_request(void *priv) { /* read DCC control register */ embeddedice_read_reg(dcc_control); - jtag_execute_queue(); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } /* check W bit */ if (buf_get_u32(dcc_control->value, 1, 1) == 1) { u32 request; - embeddedice_receive(jtag_info, &request, 1); - target_request(target, request); + if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK) + { + return retval; + } + if ((retval = target_request(target, request)) != ERROR_OK) + { + return retval; + } } } @@ -701,7 +779,10 @@ int arm7_9_poll(target_t *target) } } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } } if (target->state == TARGET_DEBUG_RUNNING) { @@ -709,7 +790,10 @@ int arm7_9_poll(target_t *target) if ((retval = arm7_9_debug_entry(target)) != ERROR_OK) return retval; - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK) + { + return retval; + } } if (target->state != TARGET_HALTED) { @@ -780,28 +864,25 @@ int arm7_9_assert_reset(target_t *target) jtag_add_reset(0, 1); } - target->state = TARGET_RESET; jtag_add_sleep(50000); armv4_5_invalidate_core_regs(target); - if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)) + if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)) { /* debug entry was already prepared in arm7_9_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; } return ERROR_OK; - } int arm7_9_deassert_reset(target_t *target) { int retval=ERROR_OK; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); - + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -919,7 +1000,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - arm7_9_clear_halt(target); + if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) + { + return retval; + } /* if the target is in Thumb state, change to ARM state */ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) @@ -932,7 +1016,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) } /* all register content is now invalid */ - armv4_5_invalidate_core_regs(target); + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) + { + return retval; + } /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); @@ -958,7 +1045,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } return ERROR_OK; } @@ -1044,7 +1134,10 @@ int arm7_9_debug_entry(target_t *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - arm7_9_clear_halt(target); + if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) + { + return retval; + } if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -1151,7 +1244,10 @@ int arm7_9_debug_entry(target_t *target) { u32 spsr; arm7_9->read_xpsr(target, &spsr, 1); - jtag_execute_queue(); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; @@ -1400,14 +1496,14 @@ int arm7_9_restart_core(struct target_s *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); } arm_jtag_set_instr(jtag_info, 0x4, NULL); - jtag_add_runtest(1, TAP_RTI); + jtag_add_runtest(1, TAP_IDLE); return jtag_execute_queue(); } @@ -1435,14 +1531,13 @@ void arm7_9_enable_breakpoints(struct target_s *target) } } - int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - int err; + int err, retval = ERROR_OK; LOG_DEBUG("-"); @@ -1461,20 +1556,39 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ if (!current) buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + u32 current_pc; + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); - arm7_9_unset_breakpoint(target, breakpoint); + if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } + + /* calculate PC of next instruction */ + u32 next_pc; + if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) + { + u32 current_opcode; + target_read_u32(target, current_pc, ¤t_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + return retval; + } LOG_DEBUG("enable single-step"); - arm7_9->enable_single_step(target); + arm7_9->enable_single_step(target, next_pc); target->debug_reason = DBG_REASON_SINGLESTEP; - arm7_9_restore_context(target); + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } if (armv4_5->core_state == ARMV4_5_STATE_ARM) arm7_9->branch_resume(target); @@ -1497,7 +1611,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ if (err != ERROR_OK) { - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } target->state = TARGET_UNKNOWN; return err; } @@ -1506,7 +1623,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } } } @@ -1514,7 +1634,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ arm7_9_enable_breakpoints(target); arm7_9_enable_watchpoints(target); - arm7_9_restore_context(target); + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } if (armv4_5->core_state == ARMV4_5_STATE_ARM) { @@ -1537,7 +1660,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0); embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); - arm7_9_restart_core(target); + if ((retval = arm7_9_restart_core(target)) != ERROR_OK) + { + return retval; + } target->debug_reason = DBG_REASON_NOTHALTED; @@ -1546,12 +1672,18 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ /* registers are now invalid */ armv4_5_invalidate_core_regs(target); target->state = TARGET_RUNNING; - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) + { + return retval; + } } else { target->state = TARGET_DEBUG_RUNNING; - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK) + { + return retval; + } } LOG_DEBUG("target resumed"); @@ -1559,24 +1691,42 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ return ERROR_OK; } -void arm7_9_enable_eice_step(target_t *target) +void arm7_9_enable_eice_step(target_t *target, u32 next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - /* setup an inverse breakpoint on the current PC - * - comparator 1 matches the current address - * - rangeout from comparator 1 is connected to comparator 0 rangein - * - comparator 0 matches any address, as long as rangein is low */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + u32 current_pc; + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + + if(next_pc != current_pc) + { + /* setup an inverse breakpoint on the current PC + * - comparator 1 matches the current address + * - rangeout from comparator 1 is connected to comparator 0 rangein + * - comparator 0 matches any address, as long as rangein is low */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + } + else + { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + } } void arm7_9_disable_eice_step(target_t *target) @@ -1600,7 +1750,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = NULL; - int err; + int err, retval; if (target->state != TARGET_HALTED) { @@ -1612,16 +1762,35 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br if (!current) buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + u32 current_pc; + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) - arm7_9_unset_breakpoint(target, breakpoint); + if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } target->debug_reason = DBG_REASON_SINGLESTEP; - arm7_9_restore_context(target); + /* calculate PC of next instruction */ + u32 next_pc; + if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) + { + u32 current_opcode; + target_read_u32(target, current_pc, ¤t_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + return retval; + } + + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } - arm7_9->enable_single_step(target); + arm7_9->enable_single_step(target, next_pc); if (armv4_5->core_state == ARMV4_5_STATE_ARM) { @@ -1637,7 +1806,10 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br return ERROR_FAIL; } - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) + { + return retval; + } err = arm7_9_execute_sys_speed(target); arm7_9->disable_single_step(target); @@ -1650,15 +1822,20 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br target->state = TARGET_UNKNOWN; } else { arm7_9_debug_entry(target); - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } LOG_DEBUG("target stepped"); } if (breakpoint) - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } return err; - } int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) @@ -1725,7 +1902,6 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod } return ERROR_OK; - } int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value) @@ -1795,7 +1971,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count arm7_9_common_t *arm7_9 = armv4_5->arch_info; u32 reg[16]; - int num_accesses = 0; + u32 num_accesses = 0; int thisrun_accesses; int i; u32 cpsr; @@ -1841,9 +2017,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4); @@ -1873,9 +2051,14 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } + } arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); @@ -1906,9 +2089,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } } arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); @@ -1961,7 +2148,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; u32 reg[16]; - int num_accesses = 0; + u32 num_accesses = 0; int thisrun_accesses; int i; u32 cpsr; @@ -2018,9 +2205,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } num_accesses += thisrun_accesses; } @@ -2050,9 +2241,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } } num_accesses += thisrun_accesses; @@ -2081,9 +2276,14 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } + } num_accesses += thisrun_accesses; @@ -2124,20 +2324,67 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_OK; } +static int dcc_count; +static u8 *dcc_buffer; + +static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info) +{ + int retval = ERROR_OK; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK) + return retval; + + int little=target->endianness==TARGET_LITTLE_ENDIAN; + int count=dcc_count; + u8 *buffer=dcc_buffer; + if (count>2) + { + /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the + * core function repeated. */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer+=4; + + embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + u8 reg_addr = ice_reg->addr & 0x1f; + jtag_tap_t *tap; + tap = ice_reg->jtag_info->tap; + + embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); + buffer += (count-2)*4; + + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + } else + { + int i; + for (i = 0; i < count; i++) + { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer += 4; + } + } + + if((retval = target_halt(target))!= ERROR_OK) + { + return retval; + } + return target_wait_state(target, TARGET_HALTED, 500); +} + static const u32 dcc_code[] = { /* MRC TST BNE MRC STR B */ 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 }; +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)); + int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - enum armv4_5_state core_state = armv4_5->core_state; - u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32); - u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); int i; if (!arm7_9->dcc_downloads) @@ -2162,78 +2409,41 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe } /* write DCC code to working area */ - target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); + if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) + { + return retval; + } } - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_state = ARMV4_5_STATE_ARM; - - arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); - - int little=target->endianness==TARGET_LITTLE_ENDIAN; - if (count>2) - { - /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the - core function repeated. - */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer+=4; + armv4_5_algorithm_t armv4_5_info; + reg_param_t reg_params[1]; - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; - int chain_pos = ice_reg->jtag_info->chain_pos; + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; - embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); - buffer += (count-2)*4; + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - } else - { - for (i = 0; i < count; i++) - { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer += 4; - } - } + buf_set_u32(reg_params[0].value, 0, 32, address); - target_halt(target); + dcc_count=count; + dcc_buffer=buffer; + retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - long long then=timeval_ms(); - int timeout; - while (!(timeout=((timeval_ms()-then)>100))) + if (retval==ERROR_OK) { - target_poll(target); - if (target->state == TARGET_HALTED) - break; - if (debug_level>=3) - { - alive_sleep(100); - } else + u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress!=(address+count*4)) { - keep_alive(); + LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress); + retval=ERROR_FAIL; } } - if (timeout) - { - LOG_ERROR("bulk write timed out, target not halted"); - return ERROR_TARGET_TIMEOUT; - } - /* restore target state */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1); - armv4_5->core_cache->reg_list[1].valid = 1; - armv4_5->core_cache->reg_list[1].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc); - armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_state = core_state; + destroy_reg_param(®_params[0]); - return ERROR_OK; + return retval; } int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) @@ -2271,7 +2481,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */ }; - int i; + u32 i; if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK) { @@ -2323,7 +2533,7 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u reg_param_t reg_params[3]; armv4_5_algorithm_t armv4_5_info; int retval; - int i; + u32 i; u32 erase_check_code[] = { @@ -2344,7 +2554,10 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++) - target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]); + if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK) + { + return retval; + } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2393,8 +2606,6 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); - register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)"); register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses "); register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, @@ -2524,12 +2735,9 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char mode = strtoul(args[1], NULL, 0); value = strtoul(args[2], NULL, 0); - arm7_9_write_core_reg(target, num, mode, value); - - return ERROR_OK; + return arm7_9_write_core_reg(target, num, mode, value); } - int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -2631,11 +2839,16 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; - arm_jtag_setup_connection(&arm7_9->jtag_info); + if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) + { + return retval; + } + arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ arm7_9->wp_available_max = 2; arm7_9->sw_breakpoints_added = 0; @@ -2664,9 +2877,15 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; - armv4_5_init_arch_info(target, armv4_5); + if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) + { + return retval; + } - target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target); + if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) + { + return retval; + } return ERROR_OK; }