X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Farm.h;h=17327899b3003e2dce86edaf23b13db68613a50f;hb=32b3859258abb97248a52e4c65b1fbce7581fab5;hp=62fbb736856352fac42ca646140cf1cd84f390eb;hpb=f18ca510b3430a515f28f19ea6c6731a40022fb6;p=fw%2Fopenocd diff --git a/src/target/arm.h b/src/target/arm.h index 62fbb7368..17327899b 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -8,6 +8,9 @@ * Copyright (C) 2009 by Øyvind Harboe * oyvind.harboe@zylin.com * + * Copyright (C) 2018 by Liviu Ionescu + * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -28,7 +31,6 @@ #include #include "target.h" - /** * @file * Holds the interface to ARM cores. @@ -38,6 +40,35 @@ * support has not yet been integrated, affecting Cortex-M parts. */ +/** + * Indicates what registers are in the ARM state core register set. + * + * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen + * on for example ARM7TDMI cores. + * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus + * three more registers are shadowed for "Secure Monitor" mode. + * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions + * and also security extensions. Additional shadowed registers for + * "Secure Monitor" and "Hypervisor" modes. + * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core, + * which only shadows SP. + */ +enum arm_core_type { + ARM_CORE_TYPE_STD = -1, + ARM_CORE_TYPE_SEC_EXT = 1, + ARM_CORE_TYPE_VIRT_EXT, + ARM_CORE_TYPE_M_PROFILE, +}; + +/** ARM Architecture specifying the version and the profile */ +enum arm_arch { + ARM_ARCH_UNKNOWN, + ARM_ARCH_V4, + ARM_ARCH_V6M, + ARM_ARCH_V7M, + ARM_ARCH_V8M, +}; + /** * Represent state of an ARM core. * @@ -58,6 +89,7 @@ enum arm_mode { ARM_MODE_SVC = 19, ARM_MODE_MON = 22, ARM_MODE_ABT = 23, + ARM_MODE_HYP = 26, ARM_MODE_UND = 27, ARM_MODE_1176_MON = 28, ARM_MODE_SYS = 31, @@ -159,15 +191,8 @@ struct arm { /** Support for arm_reg_current() */ const int *map; - /** - * Indicates what registers are in the ARM state core register set. - * ARM_MODE_ANY indicates the standard set of 37 registers, - * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three - * more registers are shadowed, for "Secure Monitor" mode. - * ARM_MODE_THREAD indicates a microcontroller profile core, - * which only shadows SP. - */ - enum arm_mode core_type; + /** Indicates what registers are in the ARM state core register set. */ + enum arm_core_type core_type; /** Record the current core mode: SVC, USR, or some other mode. */ enum arm_mode core_mode; @@ -175,38 +200,14 @@ struct arm { /** Record the current core state: ARM, Thumb, or otherwise. */ enum arm_state core_state; - /** Flag reporting unavailability of the BKPT instruction. */ - bool is_armv4; - - /** Flag reporting armv6m based core. */ - bool is_armv6m; - - /** Flag reporting whether semihosting is active. */ - bool is_semihosting; - - /** Flag reporting whether semihosting fileio is active. */ - bool is_semihosting_fileio; - - /** Flag reporting whether semihosting fileio operation is active. */ - bool semihosting_hit_fileio; + /** ARM architecture version */ + enum arm_arch arch; /** Floating point or VFP version, 0 if disabled. */ int arm_vfp_version; - /** Current semihosting operation. */ - int semihosting_op; - - /** Current semihosting result. */ - int semihosting_result; - - /** Value to be returned by semihosting SYS_ERRNO request. */ - int semihosting_errno; - int (*setup_semihosting)(struct target *target, int enable); - /** Semihosting command line. */ - char *semihosting_cmdline; - /** Backpointer to the target. */ struct target *target; @@ -230,13 +231,13 @@ struct arm { /** Read coprocessor register. */ int (*mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value); /** Write coprocessor register. */ int (*mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value); void *arch_info; @@ -251,13 +252,13 @@ struct arm { /** Convert target handle to generic ARM target state handle. */ static inline struct arm *target_to_arm(struct target *target) { - assert(target != NULL); + assert(target); return target->arch_info; } static inline bool is_arm(struct arm *arm) { - assert(arm != NULL); + assert(arm); return arm->common_magic == ARM_COMMON_MAGIC; } @@ -277,14 +278,18 @@ struct arm_reg { }; struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm); +void arm_free_reg_cache(struct arm *arm); + struct reg_cache *armv8_build_reg_cache(struct target *target); extern const struct command_registration arm_command_handlers[]; int arm_arch_state(struct target *target); +const char *arm_get_gdb_arch(struct target *target); int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); +const char *armv8_get_gdb_arch(struct target *target); int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); @@ -308,7 +313,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum); int arm_blank_check_memory(struct target *target, - target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value); + struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); void arm_set_cpsr(struct arm *arm, uint32_t cpsr); struct reg *arm_reg_current(struct arm *arm, unsigned regnum);