X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Ftarget%2Fadi_v5_jtag.c;h=9f37bd553d841080b8c416eceed2c553d2f1e524;hb=077d77140ca7aaff3f301c33f20f3831d0913c11;hp=8731a1a0970e6e9686108d8d114a36b71bdc1cb0;hpb=441ea95f693316052f04486b927abb2b152ca547;p=fw%2Fopenocd diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index 8731a1a09..9f37bd553 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -40,7 +40,6 @@ #include "arm_adi_v5.h" #include - /* JTAG instructions/registers for JTAG-DP and SWJ-DP */ #define JTAG_DP_ABORT 0x8 #define JTAG_DP_DPACC 0xA @@ -191,22 +190,30 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) /* too expensive to call keep_alive() here */ -#if 0 - /* Danger!!!! BROKEN!!!! */ - adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? - R956 introduced the check on return value here and now Michael Schwingen reports - that this code no longer works.... - - https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html - */ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_ERROR("BUG: Why does this fail the first time????"); - } - /* Why??? second time it works??? */ -#endif + /* Here be dragons! + * + * It is easy to be in a JTAG clock range where the target + * is not operating in a stable fashion. This happens + * for a few reasons: + * + * - the user may construct a simple test case to try to see + * if a higher JTAG clock works to eke out more performance. + * This simple case may pass, but more complex situations can + * fail. + * + * - The mostly works JTAG clock rate and the complete failure + * JTAG clock rate may be as much as 2-4x apart. This seems + * to be especially true on RC oscillator driven parts. + * + * So: even if calling adi_jtag_scan_inout_check_u32() multiple + * times here seems to "make things better here", it is just + * hiding problems with too high a JTAG clock. + * + * Note that even if some parts have RCLK/RTCK, that doesn't + * mean that RCLK/RTCK is the *correct* rate to run the JTAG + * interface at, i.e. RCLK/RTCK rates can be "too high", especially + * before the RC oscillator phase is not yet complete. + */ /* Post CTRL/STAT read; discard any previous posted read value * but collect its ACK status. @@ -215,22 +222,19 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; dap->ack = dap->ack & 0x7; /* common code path avoids calling timeval_ms() */ - if (dap->ack != JTAG_ACK_OK_FAULT) - { + if (dap->ack != JTAG_ACK_OK_FAULT) { long long then = timeval_ms(); - while (dap->ack != JTAG_ACK_OK_FAULT) - { - if (dap->ack == JTAG_ACK_WAIT) - { - if ((timeval_ms()-then) > 1000) - { + while (dap->ack != JTAG_ACK_OK_FAULT) { + if (dap->ack == JTAG_ACK_WAIT) { + if ((timeval_ms()-then) > 1000) { /* NOTE: this would be a good spot * to use JTAG_DP_ABORT. */ @@ -239,9 +243,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) "in JTAG-DP transaction"); return ERROR_JTAG_DEVICE_ERROR; } - } - else - { + } else { LOG_WARNING("Invalid ACK %#x " "in JTAG-DP transaction", dap->ack); @@ -252,7 +254,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; dap->ack = dap->ack & 0x7; } @@ -261,18 +264,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */ /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) - { + if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat); /* Check power to debug regions */ - if ((ctrlstat & 0xf0000000) != 0xf0000000) - { + if ((ctrlstat & 0xf0000000) != 0xf0000000) { retval = ahbap_debugport_init(dap); if (retval != ERROR_OK) return retval; - } - else - { + } else { uint32_t mem_ap_csw, mem_ap_tar; /* Maybe print information about last intended @@ -306,7 +305,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat); @@ -321,13 +321,15 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32, mem_ap_csw, mem_ap_tar); } - if ((retval = dap_run(dap)) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -384,7 +386,7 @@ static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg) return ERROR_OK; dap->ap_bank_value = select_ap_bank; - select_ap_bank |= dap->apsel; + select_ap_bank |= dap->ap_current; return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank); }