X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstmf0%2Fao_timer.c;h=50fd67b8517e6fc7119ad9225c140605e5d30f2a;hb=65bb93f69b2f420281b67d62a9ee3cf30874fb7c;hp=d3542a57c153ba8a737516b17ad36d3208674a79;hpb=a5607aad694c01c01c48229172b289f005a1b6bb;p=fw%2Faltos

diff --git a/src/stmf0/ao_timer.c b/src/stmf0/ao_timer.c
index d3542a57..50fd67b8 100644
--- a/src/stmf0/ao_timer.c
+++ b/src/stmf0/ao_timer.c
@@ -3,7 +3,8 @@
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -50,12 +51,14 @@ void stm_systick_isr(void)
 #if AO_DATA_ALL
 		if (++ao_data_count == ao_data_interval) {
 			ao_data_count = 0;
+#if HAS_ADC
 #if HAS_FAKE_FLIGHT
 			if (ao_fake_flight_active)
 				ao_fake_flight_poll();
 			else
 #endif
 				ao_adc_poll();
+#endif
 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
 			ao_wakeup((void *) &ao_data_count);
 #endif
@@ -83,6 +86,7 @@ ao_timer_set_adc_interval(uint8_t interval)
 void
 ao_timer_init(void)
 {
+	stm_systick.csr = 0;
 	stm_systick.rvr = SYSTICK_RELOAD;
 	stm_systick.cvr = 0;
 	stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
@@ -92,6 +96,7 @@ ao_timer_init(void)
 
 #endif
 
+#if AO_HSI48
 static void
 ao_clock_enable_crs(void)
 {
@@ -128,6 +133,7 @@ ao_clock_enable_crs(void)
 		      (0 << STM_CRS_CR_SYNCWARNIE) |
 		      (0 << STM_CRS_CR_SYNCOKIE));
 }
+#endif
 
 static void
 ao_clock_hsi(void)
@@ -155,10 +161,11 @@ static void
 ao_clock_normal_start(void)
 {
 #if AO_HSE
-#define STM_RCC_CFGR_SWS_TARGET_CLOCK		STM_RCC_CFGR_SWS_HSE
-#define STM_RCC_CFGR_SW_TARGET_CLOCK		STM_RCC_CFGR_SW_HSE
+	uint32_t	cfgr;
+#define STM_RCC_CFGR_SWS_TARGET_CLOCK		STM_RCC_CFGR_SWS_PLL
+#define STM_RCC_CFGR_SW_TARGET_CLOCK		STM_RCC_CFGR_SW_PLL
 #define STM_PLLSRC				AO_HSE
-#define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK	1
+#define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK	STM_RCC_CFGR_PLLSRC_HSE
 
 #if AO_HSE_BYPASS
 	stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
@@ -170,12 +177,30 @@ ao_clock_normal_start(void)
 	while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
 		asm("nop");
 
-#ifdef STM_PLLSRC
-#error No code for PLL initialization yet
-#endif
+	/* Disable the PLL */
+	stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
+	while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
+		asm("nop");
 
-#endif
+	/* Set multiplier */
+	cfgr = stm_rcc.cfgr;
+	cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
+	cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
+
+	/* PLL source */
+	cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
+	cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK  << STM_RCC_CFGR_PLLSRC);
+	stm_rcc.cfgr = cfgr;
 
+	/* Set pre divider */
+	stm_rcc.cfgr2 = (AO_RCC_CFGR2_PLLDIV << STM_RCC_CFGR2_PREDIV);
+
+	/* Enable the PLL and wait for it */
+	stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
+	while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
+		asm("nop");
+
+#endif
 
 #if AO_HSI48
 #define STM_RCC_CFGR_SWS_TARGET_CLOCK		STM_RCC_CFGR_SWS_HSI48
@@ -198,6 +223,8 @@ ao_clock_normal_start(void)
 #define STM_PLLSRC				STM_HSI
 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK	0
 #endif
+
+
 }
 
 static void
@@ -223,6 +250,10 @@ ao_clock_normal_switch(void)
 	/* Turn off the HSI clock */
 	stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
 #endif
+#ifdef STM_PLLSRC
+	/* USB PLL source */
+	stm_rcc.cfgr3 |= (1 << STM_RCC_CFGR3_USBSW);
+#endif
 }
 
 void
@@ -271,14 +302,34 @@ ao_clock_init(void)
 	/* Clear reset flags */
 	stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 
+#ifdef AO_MCO_PORT
+	cfgr = stm_rcc.cfgr;
+
+	/* Send PLL clock to MCO */
+	cfgr &= ~(STM_RCC_CFGR_MCO_MASK << STM_RCC_CFGR_MCO);
+	cfgr |= (STM_RCC_CFGR_MCO_PLLCLK << STM_RCC_CFGR_MCO);
+
+	/* Divide by 1 */
+	cfgr &= ~(STM_RCC_CFGR_MCOPRE_DIV_MASK << STM_RCC_CFGR_MCOPRE);
+	cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
+
+	/* Don't divide PLL */
+	cfgr |= (1 << STM_RCC_CFGR_PLL_NODIV);
+
+	stm_rcc.cfgr = cfgr;
+
+	ao_enable_port(AO_MCO_PORT);
+	stm_ospeedr_set(AO_MCO_PORT, AO_MCO_PIN, STM_OSPEEDR_HIGH);
+	stm_afr_set(AO_MCO_PORT, AO_MCO_PIN, AO_MCO_AF);
+#endif
+
 #if DEBUG_THE_CLOCK
 	/* Output SYSCLK on PA8 for measurments */
 
 	stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
 
 	stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
-	stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
-	stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
+	stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
 
 	stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
 	stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);