X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm32f1%2Fstm32f1.h;fp=src%2Fstm32f1%2Fstm32f1.h;h=cf7d0460b96d1c34b31019ef89c996e8c4837bf6;hb=5530d7b305157a8027ea7f83152a526dec16c546;hp=ba6f4db3550bdfb92401d9bbe046441dcd09172a;hpb=36ec68007ceaaa245e82982a031a63a2ddf3f07d;p=fw%2Faltos diff --git a/src/stm32f1/stm32f1.h b/src/stm32f1/stm32f1.h index ba6f4db3..cf7d0460 100644 --- a/src/stm32f1/stm32f1.h +++ b/src/stm32f1/stm32f1.h @@ -777,7 +777,209 @@ union stm_usb_bdt { extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4))); -//#define stm_usb_sram ((uint8_t *)0x40006000); +//#define stm_usb_sram ((uint8_t *)0x40006000) + +struct stm_dma_channel { + vuint32_t ccr; + vuint32_t cndtr; + vvoid_t cpar; + vvoid_t cmar; + vuint32_t reserved; +}; + +#define STM_NUM_DMA 7 + +struct stm_dma { + vuint32_t isr; + vuint32_t ifcr; + struct stm_dma_channel channel[STM_NUM_DMA]; +}; + +extern struct stm_dma stm_dma; + +#define stm_dma (*((struct stm_dma *) 0x40020000)) + +/* DMA channels go from 1 to 7, instead of 0 to 6 (sigh) + */ + +#define STM_DMA_INDEX(channel) ((channel) - 1) + +#define STM_DMA_ISR(index) ((index) << 2) +#define STM_DMA_ISR_MASK 0xfUL +#define STM_DMA_ISR_TEIF 3 +#define STM_DMA_ISR_HTIF 2 +#define STM_DMA_ISR_TCIF 1 +#define STM_DMA_ISR_GIF 0 + +#define STM_DMA_IFCR(index) ((index) << 2) +#define STM_DMA_IFCR_MASK 0xfUL +#define STM_DMA_IFCR_CTEIF 3 +#define STM_DMA_IFCR_CHTIF 2 +#define STM_DMA_IFCR_CTCIF 1 +#define STM_DMA_IFCR_CGIF 0 + +#define STM_DMA_CCR_MEM2MEM (14) + +#define STM_DMA_CCR_PL (12) +#define STM_DMA_CCR_PL_LOW (0) +#define STM_DMA_CCR_PL_MEDIUM (1) +#define STM_DMA_CCR_PL_HIGH (2) +#define STM_DMA_CCR_PL_VERY_HIGH (3) +#define STM_DMA_CCR_PL_MASK (3) + +#define STM_DMA_CCR_MSIZE (10) +#define STM_DMA_CCR_MSIZE_8 (0) +#define STM_DMA_CCR_MSIZE_16 (1) +#define STM_DMA_CCR_MSIZE_32 (2) +#define STM_DMA_CCR_MSIZE_MASK (3) + +#define STM_DMA_CCR_PSIZE (8) +#define STM_DMA_CCR_PSIZE_8 (0) +#define STM_DMA_CCR_PSIZE_16 (1) +#define STM_DMA_CCR_PSIZE_32 (2) +#define STM_DMA_CCR_PSIZE_MASK (3) + +#define STM_DMA_CCR_MINC (7) +#define STM_DMA_CCR_PINC (6) +#define STM_DMA_CCR_CIRC (5) +#define STM_DMA_CCR_DIR (4) +#define STM_DMA_CCR_DIR_PER_TO_MEM 0 +#define STM_DMA_CCR_DIR_MEM_TO_PER 1 +#define STM_DMA_CCR_TEIE (3) +#define STM_DMA_CCR_HTIE (2) +#define STM_DMA_CCR_TCIE (1) +#define STM_DMA_CCR_EN (0) + +#define STM_DMA_CHANNEL_ADC1 1 +#define STM_DMA_CHANNEL_SPI1_RX 2 +#define STM_DMA_CHANNEL_SPI1_TX 3 +#define STM_DMA_CHANNEL_SPI2_RX 4 +#define STM_DMA_CHANNEL_SPI2_TX 5 +#define STM_DMA_CHANNEL_USART3_TX 2 +#define STM_DMA_CHANNEL_USART3_RX 3 +#define STM_DMA_CHANNEL_USART1_TX 4 +#define STM_DMA_CHANNEL_USART1_RX 5 +#define STM_DMA_CHANNEL_USART2_RX 6 +#define STM_DMA_CHANNEL_USART2_TX 7 +#define STM_DMA_CHANNEL_I2C2_TX 4 +#define STM_DMA_CHANNEL_I2C2_RX 5 +#define STM_DMA_CHANNEL_I2C1_TX 6 +#define STM_DMA_CHANNEL_I2C1_RX 7 +#define STM_DMA_CHANNEL_TIM1_CH1 2 +#define STM_DMA_CHANNEL_TIM1_CH4 4 +#define STM_DMA_CHANNEL_TIM1_TRIG 4 +#define STM_DMA_CHANNEL_TIM1_COM 4 +#define STM_DMA_CHANNEL_TIM1_UP 5 +#define STM_DMA_CHANNEL_TIM1_CH3 6 +#define STM_DMA_CHANNEL_TIM2_CH3 1 +#define STM_DMA_CHANNEL_TIM2_UP 2 +#define STM_DMA_CHANNEL_TIM2_CH1 5 +#define STM_DMA_CHANNEL_TIM2_CH2 7 +#define STM_DMA_CHANNEL_TIM2_CH4 7 +#define STM_DMA_CHANNEL_TIM3_CH3 2 +#define STM_DMA_CHANNEL_TIM3_CH4 3 +#define STM_DMA_CHANNEL_TIM3_UP 3 +#define STM_DMA_CHANNEL_TIM3_CH1 6 +#define STM_DMA_CHANNEL_TIM3_TRIG 6 +#define STM_DMA_CHANNEL_TIM4_CH1 1 +#define STM_DMA_CHANNEL_TIM4_CH2 4 +#define STM_DMA_CHANNEL_TIM4_CH3 5 +#define STM_DMA_CHANNEL_TIM4_UP 7 + +/* high density, xl-density and connectivity devices also have dma2 */ + +#define STM_DMA2_CHANNEL_ADC3 5 +#define STM_DMA2_CHANNEL_SPI3_RX 1 +#define STM_DMA2_CHANNEL_SPI3_TX 2 +#define STM_DMA2_CHANNEL_UART4_RX 3 +#define STM_DMA2_CHANNEL_UART4_TX 5 +#define STM_DMA2_CHANNEL_TIM5_CH4 1 +#define STM_DMA2_CHANNEL_TIM5_TRIG 1 +#define STM_DMA2_CHANNEL_TIM5_CH3 2 +#define STM_DMA2_CHANNEL_TIM5_UP 2 +#define STM_DMA2_CHANNEL_TIM5_CH2 4 +#define STM_DMA2_CHANNEL_TIM5_CH1 5 +#define STM_DMA2_CHANNEL_TIM6_UP 3 +#define STM_DMA2_CHANNEL_DAC_CHANNEL1 3 +#define STM_DMA2_CHANNEL_TIM7_UP 4 +#define STM_DMA2_CHANNEL_DAC_CHANNEL2 4 +#define STM_DMA2_CHANNEL_TIM8_CH3 1 +#define STM_DMA2_CHANNEL_TIM8_UP 1 +#define STM_DMA2_CHANNEL_TIM8_CH4 2 +#define STM_DMA2_CHANNEL_TIM8_TRIG 2 +#define STM_DMA2_CHANNEL_TIM8_COM 2 +#define STM_DMA2_CHANNEL_TIM8_CH1 3 +#define STM_DMA2_CHANNEL_TIM8_CH2 5 + +struct stm_spi { + vuint32_t cr1; + vuint32_t cr2; + vuint32_t sr; + vuint32_t dr; + + vuint32_t crcpr; + vuint32_t rxcrcr; + vuint32_t txcrcr; + vuint32_t i2scfgr; + + vuint32_t i2spr; +}; + +extern struct stm_spi stm_spi1, stm_spi2; + +//#define stm_spi1 (*((struct stm_spi *) 0x40013000)) +//#define stm_spi2 (*((struct stm_spi *) 0x40003800)) + +/* SPI channels go from 1 to 2, instead of 0 to 1 (sigh) + */ + +#define STM_NUM_SPI 2 + +#define STM_SPI_INDEX(channel) ((channel) - 1) + +#define STM_SPI_CR1_BIDIMODE 15 +#define STM_SPI_CR1_BIDIOE 14 +#define STM_SPI_CR1_CRCEN 13 +#define STM_SPI_CR1_CRCNEXT 12 +#define STM_SPI_CR1_DFF 11 +#define STM_SPI_CR1_RXONLY 10 +#define STM_SPI_CR1_SSM 9 +#define STM_SPI_CR1_SSI 8 +#define STM_SPI_CR1_LSBFIRST 7 +#define STM_SPI_CR1_SPE 6 +#define STM_SPI_CR1_BR 3 +#define STM_SPI_CR1_BR_PCLK_2 0 +#define STM_SPI_CR1_BR_PCLK_4 1 +#define STM_SPI_CR1_BR_PCLK_8 2 +#define STM_SPI_CR1_BR_PCLK_16 3 +#define STM_SPI_CR1_BR_PCLK_32 4 +#define STM_SPI_CR1_BR_PCLK_64 5 +#define STM_SPI_CR1_BR_PCLK_128 6 +#define STM_SPI_CR1_BR_PCLK_256 7 +#define STM_SPI_CR1_BR_MASK 7UL + +#define STM_SPI_CR1_MSTR 2 +#define STM_SPI_CR1_CPOL 1 +#define STM_SPI_CR1_CPHA 0 + +#define STM_SPI_CR2_TXEIE 7 +#define STM_SPI_CR2_RXNEIE 6 +#define STM_SPI_CR2_ERRIE 5 +#define STM_SPI_CR2_SSOE 2 +#define STM_SPI_CR2_TXDMAEN 1 +#define STM_SPI_CR2_RXDMAEN 0 + +#define STM_SPI_SR_FRE 8 +#define STM_SPI_SR_BSY 7 +#define STM_SPI_SR_OVR 6 +#define STM_SPI_SR_MODF 5 +#define STM_SPI_SR_CRCERR 4 +#define STM_SPI_SR_UDR 3 +#define STM_SPI_SR_CHSIDE 2 +#define STM_SPI_SR_TXE 1 +#define STM_SPI_SR_RXNE 0 + + #define isr_decl(name) void stm_ ## name ## _isr(void)