X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm32f1%2Fao_clock.c;h=c203b01286f6074ff03b3637097e450c41538d65;hb=96459ad1231898c743aacf3fbc1afbf92f5579dc;hp=1ce32a90343c8838c5df9435d3bd0069abaf6771;hpb=d2cb18542f4f6071232bd046fd1b257228c17a25;p=fw%2Faltos

diff --git a/src/stm32f1/ao_clock.c b/src/stm32f1/ao_clock.c
index 1ce32a90..c203b012 100644
--- a/src/stm32f1/ao_clock.c
+++ b/src/stm32f1/ao_clock.c
@@ -69,16 +69,12 @@ ao_clock_init(void)
 		asm("nop");
 #endif
 
-#if 0
-	/* Set flash latency to tolerate 32MHz SYSCLK  -> 1 wait state */
+	/* Set flash latency to tolerate 72MHz SYSCLK  -> 2 wait states */
 
 	/* Enable 64-bit access and prefetch */
-	stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
-	stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
-
-	/* Enable 1 wait state so the CPU can run at 32MHz */
-	stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
-#endif
+	stm_flash.acr = ((1 << STM_FLASH_ACR_PRFTBE) |
+			 (0 << STM_FLASH_ACR_HLFCYA) |
+			 (STM_FLASH_ACR_LATENCY_2 << STM_FLASH_ACR_LATENCY));
 
 	/* Enable power interface clock */
 	stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);