X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm32f1%2Fao_clock.c;h=3fcf33b81177da379087fdbd72c315b83a95162f;hb=cea7122fc1843b14a179ed9311677f69c10b38eb;hp=1ce32a90343c8838c5df9435d3bd0069abaf6771;hpb=d2cb18542f4f6071232bd046fd1b257228c17a25;p=fw%2Faltos

diff --git a/src/stm32f1/ao_clock.c b/src/stm32f1/ao_clock.c
index 1ce32a90..3fcf33b8 100644
--- a/src/stm32f1/ao_clock.c
+++ b/src/stm32f1/ao_clock.c
@@ -69,16 +69,12 @@ ao_clock_init(void)
 		asm("nop");
 #endif
 
-#if 0
-	/* Set flash latency to tolerate 32MHz SYSCLK  -> 1 wait state */
+	/* Set flash latency to tolerate 72MHz SYSCLK  -> 2 wait states */
 
 	/* Enable 64-bit access and prefetch */
-	stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
-	stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
-
-	/* Enable 1 wait state so the CPU can run at 32MHz */
-	stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
-#endif
+	stm_flash.acr = ((1 << STM_FLASH_ACR_PRFTBE) |
+			 (0 << STM_FLASH_ACR_HLFCYA) |
+			 (STM_FLASH_ACR_LATENCY_2 << STM_FLASH_ACR_LATENCY));
 
 	/* Enable power interface clock */
 	stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
@@ -127,12 +123,15 @@ ao_clock_init(void)
 	while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
 		asm("nop");
 
-	/* PLLVCO */
+	/* PLLMUL */
 	cfgr = stm_rcc.cfgr;
 	cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
-
 	cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
 
+	/* PLLXTPRE */
+	cfgr &= ~(STM_RCC_CFGR_PLLXTPRE_MASK << STM_RCC_CFGR_PLLXTPRE);
+	cfgr |= (AO_RCC_CFGR_PLLXTPRE << STM_RCC_CFGR_PLLXTPRE);
+
 	/* PLL source */
 	cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
 	cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;