X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=a20efa8a1b0c31f52bfa5536752f607d36ad4b3a;hb=a487d2fcba57141f6b083d5612c76bac5ad1ac7c;hp=1d6360372e9a51c604bc059b88b8961f27ffc4fb;hpb=760b1f02c178c600226f39b5e66d8cbadbf4a29b;p=fw%2Faltos diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h index 1d636037..a20efa8a 100644 --- a/src/stm/stm32l.h +++ b/src/stm/stm32l.h @@ -3,7 +3,8 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of @@ -52,7 +53,7 @@ stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) { value << STM_MODER_SHIFT(pin)); } -static inline vuint32_t +static inline uint32_t stm_moder_get(struct stm_gpio *gpio, int pin) { return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK; } @@ -69,7 +70,7 @@ stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) { value << STM_OTYPER_SHIFT(pin)); } -static inline vuint32_t +static inline uint32_t stm_otyper_get(struct stm_gpio *gpio, int pin) { return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK; } @@ -88,7 +89,7 @@ stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) { value << STM_OSPEEDR_SHIFT(pin)); } -static inline vuint32_t +static inline uint32_t stm_ospeedr_get(struct stm_gpio *gpio, int pin) { return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK; } @@ -166,17 +167,47 @@ stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) { gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin); } +static inline void +stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) { + gpio->bsrr = bits; +} + +static inline void +stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) { + gpio->bsrr = ((uint32_t) bits) << 16; +} + static inline uint8_t stm_gpio_get(struct stm_gpio *gpio, int pin) { return (gpio->idr >> pin) & 1; } -extern struct stm_gpio stm_gpioa; -extern struct stm_gpio stm_gpiob; -extern struct stm_gpio stm_gpioc; -extern struct stm_gpio stm_gpiod; -extern struct stm_gpio stm_gpioe; -extern struct stm_gpio stm_gpioh; +static inline uint16_t +stm_gpio_get_all(struct stm_gpio *gpio) { + return gpio->idr; +} + +/* + * We can't define these in registers.ld or our fancy + * ao_enable_gpio macro will expand into a huge pile of code + * as the compiler won't do correct constant folding and + * dead-code elimination + + extern struct stm_gpio stm_gpioa; + extern struct stm_gpio stm_gpiob; + extern struct stm_gpio stm_gpioc; + extern struct stm_gpio stm_gpiod; + extern struct stm_gpio stm_gpioe; + extern struct stm_gpio stm_gpioh; + +*/ + +#define stm_gpioh (*((struct stm_gpio *) 0x40021400)) +#define stm_gpioe (*((struct stm_gpio *) 0x40021000)) +#define stm_gpiod (*((struct stm_gpio *) 0x40020c00)) +#define stm_gpioc (*((struct stm_gpio *) 0x40020800)) +#define stm_gpiob (*((struct stm_gpio *) 0x40020400)) +#define stm_gpioa (*((struct stm_gpio *) 0x40020000)) struct stm_usart { vuint32_t sr; /* status register */ @@ -435,6 +466,9 @@ extern struct stm_flash stm_flash; #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF #define STM_FLASH_PEKEYR_PEKEY2 0x02030405 +#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF +#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516 + struct stm_rcc { vuint32_t cr; vuint32_t icscr; @@ -484,7 +518,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOPRE_DIV_4 2 #define STM_RCC_CFGR_MCOPRE_DIV_8 3 #define STM_RCC_CFGR_MCOPRE_DIV_16 4 -#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7 +#define STM_RCC_CFGR_MCOPRE_MASK 7 #define STM_RCC_CFGR_MCOSEL (24) #define STM_RCC_CFGR_MCOSEL_DISABLE 0 @@ -811,6 +845,24 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CLR_UDDC (3) #define STM_LCD_CLR_SOFC (1) +/* The SYSTICK starts at 0xe000e010 */ + +struct stm_systick { + vuint32_t csr; + vuint32_t rvr; + vuint32_t cvr; + vuint32_t calib; +}; + +extern struct stm_systick stm_systick; + +#define STM_SYSTICK_CSR_ENABLE 0 +#define STM_SYSTICK_CSR_TICKINT 1 +#define STM_SYSTICK_CSR_CLKSOURCE 2 +#define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0 +#define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1 +#define STM_SYSTICK_CSR_COUNTFLAG 16 + /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */ struct stm_nvic { @@ -845,7 +897,11 @@ struct stm_nvic { vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */ vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */ - uint8_t _unusedc18[0xe00 - 0xc18]; + vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */ + vuint32_t shpr11_8; /* 0xc1c */ + vuint32_t shpr15_12; /* 0xc20 */ + + uint8_t _unusedc18[0xe00 - 0xc24]; vuint32_t stir; /* 0xe00 */ }; @@ -1308,10 +1364,13 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR2_TXDMAEN 1 #define STM_SPI_CR2_RXDMAEN 0 +#define STM_SPI_SR_FRE 8 #define STM_SPI_SR_BSY 7 #define STM_SPI_SR_OVR 6 #define STM_SPI_SR_MODF 5 #define STM_SPI_SR_CRCERR 4 +#define STM_SPI_SR_UDR 3 +#define STM_SPI_SR_CHSIDE 2 #define STM_SPI_SR_TXE 1 #define STM_SPI_SR_RXNE 0 @@ -1466,6 +1525,36 @@ extern struct stm_temp_cal stm_temp_cal; #define stm_temp_cal_cold 25 #define stm_temp_cal_hot 110 +struct stm_dbg_mcu { + uint32_t idcode; +}; + +extern struct stm_dbg_mcu stm_dbg_mcu; + +static inline uint16_t +stm_dev_id(void) { + return stm_dbg_mcu.idcode & 0xfff; +} + +struct stm_flash_size { + uint16_t f_size; +}; + +extern struct stm_flash_size stm_flash_size_medium; +extern struct stm_flash_size stm_flash_size_large; + +/* Returns flash size in bytes */ +extern uint32_t +stm_flash_size(void); + +struct stm_device_id { + uint32_t u_id0; + uint32_t u_id1; + uint32_t u_id2; +}; + +extern struct stm_device_id stm_device_id; + #define STM_NUM_I2C 2 #define STM_I2C_INDEX(channel) ((channel) - 1) @@ -1509,6 +1598,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CR2_FREQ_4_MHZ 4 #define STM_I2C_CR2_FREQ_8_MHZ 8 #define STM_I2C_CR2_FREQ_16_MHZ 16 +#define STM_I2C_CR2_FREQ_24_MHZ 24 #define STM_I2C_CR2_FREQ_32_MHZ 32 #define STM_I2C_CR2_FREQ_MASK 0x3f @@ -1655,6 +1745,12 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7 #define STM_TIM234_SMCR_SMS_MASK 7 +#define STM_TIM234_DIER_CC4IE 4 +#define STM_TIM234_DIER_CC3IE 3 +#define STM_TIM234_DIER_CC2IE 2 +#define STM_TIM234_DIER_CC1IE 1 +#define STM_TIM234_DIER_UIE 0 + #define STM_TIM234_SR_CC4OF 12 #define STM_TIM234_SR_CC3OF 11 #define STM_TIM234_SR_CC2OF 10 @@ -1704,7 +1800,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7 #define STM_TIM234_CCMR1_OC1M_MASK 7 -#define STM_TIM234_CCMR1_OC1PE 11 +#define STM_TIM234_CCMR1_OC1PE 3 #define STM_TIM234_CCMR1_OC1FE 2 #define STM_TIM234_CCMR1_CC1S 0 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0 @@ -1713,7 +1809,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 #define STM_TIM234_CCMR1_CC1S_MASK 3 -#define STM_TIM234_CCMR2_OC2CE 15 +#define STM_TIM234_CCMR2_OC4CE 15 #define STM_TIM234_CCMR2_OC4M 12 #define STM_TIM234_CCMR2_OC4M_FROZEN 0 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 @@ -1744,7 +1840,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7 #define STM_TIM234_CCMR2_OC3M_MASK 7 -#define STM_TIM234_CCMR2_OC3PE 11 +#define STM_TIM234_CCMR2_OC3PE 3 #define STM_TIM234_CCMR2_OC3FE 2 #define STM_TIM234_CCMR2_CC3S 0 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0 @@ -1755,15 +1851,23 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCER_CC4NP 15 #define STM_TIM234_CCER_CC4P 13 +#define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC4E 12 #define STM_TIM234_CCER_CC3NP 11 #define STM_TIM234_CCER_CC3P 9 +#define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC3E 8 #define STM_TIM234_CCER_CC2NP 7 #define STM_TIM234_CCER_CC2P 5 +#define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC2E 4 #define STM_TIM234_CCER_CC1NP 3 #define STM_TIM234_CCER_CC1P 1 +#define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0 +#define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC1E 0 struct stm_usb { @@ -1876,7 +1980,7 @@ union stm_usb_bdt { #define STM_USB_BDT_SIZE 8 -extern uint8_t stm_usb_sram[]; +extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4))); struct stm_exti { vuint32_t imr;