X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=0dbfae39814c0fd4a5e43805bbbe66c120800ce9;hb=e57ab2a7bfb69c0ef9b5b7fa8e53e20a500e7c6c;hp=e950d09bf5b8b905b6b32d7e37c290ce549ba696;hpb=b119e19604aa557a40e848c60d98a67b5f259bbd;p=fw%2Faltos

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index e950d09b..0dbfae39 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -901,6 +901,93 @@ stm_nvic_get_priority(int irq) {
 	return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 }
 
+struct stm_scb {
+	vuint32_t	cpuid;
+	vuint32_t	icsr;
+	vuint32_t	vtor;
+	vuint32_t	aircr;
+
+	vuint32_t	scr;
+	vuint32_t	ccr;
+	vuint32_t	shpr1;
+	vuint32_t	shpr2;
+
+	vuint32_t	shpr3;
+	vuint32_t	shcrs;
+	vuint32_t	cfsr;
+	vuint32_t	hfsr;
+
+	uint32_t	unused_30;
+	vuint32_t	mmfar;
+	vuint32_t	bfar;
+};
+
+extern struct stm_scb stm_scb;
+
+#define STM_SCB_AIRCR_VECTKEY		16
+#define  STM_SCB_AIRCR_VECTKEY_KEY		0x05fa
+#define STM_SCB_AIRCR_PRIGROUP		8
+#define STM_SCB_AIRCR_SYSRESETREQ	2
+#define STM_SCB_AIRCR_VECTCLRACTIVE	1
+#define STM_SCB_AIRCR_VECTRESET		0
+
+struct stm_mpu {
+	vuint32_t	typer;
+	vuint32_t	cr;
+	vuint32_t	rnr;
+	vuint32_t	rbar;
+
+	vuint32_t	rasr;
+	vuint32_t	rbar_a1;
+	vuint32_t	rasr_a1;
+	vuint32_t	rbar_a2;
+	vuint32_t	rasr_a2;
+	vuint32_t	rbar_a3;
+	vuint32_t	rasr_a3;
+};
+
+extern struct stm_mpu stm_mpu;
+
+#define STM_MPU_TYPER_IREGION	16
+#define  STM_MPU_TYPER_IREGION_MASK	0xff
+#define STM_MPU_TYPER_DREGION	8
+#define  STM_MPU_TYPER_DREGION_MASK	0xff
+#define STM_MPU_TYPER_SEPARATE	0
+
+#define STM_MPU_CR_PRIVDEFENA	2
+#define STM_MPU_CR_HFNMIENA	1
+#define STM_MPU_CR_ENABLE	0
+
+#define STM_MPU_RNR_REGION	0
+#define STM_MPU_RNR_REGION_MASK		0xff
+
+#define STM_MPU_RBAR_ADDR	5
+#define STM_MPU_RBAR_ADDR_MASK		0x7ffffff
+
+#define STM_MPU_RBAR_VALID	4
+#define STM_MPU_RBAR_REGION	0
+#define STM_MPU_RBAR_REGION_MASK	0xf
+
+#define STM_MPU_RASR_XN		28
+#define STM_MPU_RASR_AP		24
+#define  STM_MPU_RASR_AP_NONE_NONE	0
+#define  STM_MPU_RASR_AP_RW_NONE	1
+#define  STM_MPU_RASR_AP_RW_RO		2
+#define  STM_MPU_RASR_AP_RW_RW		3
+#define  STM_MPU_RASR_AP_RO_NONE	5
+#define  STM_MPU_RASR_AP_RO_RO		6
+#define  STM_MPU_RASR_AP_MASK		7
+#define STM_MPU_RASR_TEX	19
+#define  STM_MPU_RASR_TEX_MASK		7
+#define STM_MPU_RASR_S		18
+#define STM_MPU_RASR_C		17
+#define STM_MPU_RASR_B		16
+#define STM_MPU_RASR_SRD	8
+#define  STM_MPU_RASR_SRD_MASK		0xff
+#define STM_MPU_RASR_SIZE	1
+#define  STM_MPU_RASR_SIZE_MASK		0x1f
+#define STM_MPU_RASR_ENABLE	0
+
 #define isr(name) void stm_ ## name ## _isr(void);
 
 isr(nmi)
@@ -1568,6 +1655,13 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
 #define STM_TIM234_SR_CC1IF	1
 #define STM_TIM234_SR_UIF	0
 
+#define STM_TIM234_EGR_TG	6
+#define STM_TIM234_EGR_CC4G	4
+#define STM_TIM234_EGR_CC3G	3
+#define STM_TIM234_EGR_CC2G	2
+#define STM_TIM234_EGR_CC1G	1
+#define STM_TIM234_EGR_UG	0
+
 #define STM_TIM234_CCMR1_OC2CE	15
 #define STM_TIM234_CCMR1_OC2M	12
 #define  STM_TIM234_CCMR1_OC2M_FROZEN			0