X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fao_timer.c;h=91ede84bcc5ee7f4e015fb46b6188412c35b6746;hb=5ab4a8b911e254dc829b61cb0abc9fd0b46b84b3;hp=5976eb3f6657b6882d8cbfc668524f646f8387f4;hpb=091582c446319fe4a79154153ece5372b2faec83;p=fw%2Faltos

diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index 5976eb3f..91ede84b 100644
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -17,7 +17,15 @@
 
 #include "ao.h"
 #include <ao_task.h>
+#if HAS_FAKE_FLIGHT
+#include <ao_fake_flight.h>
+#endif
+
+#ifndef HAS_TICK
+#define HAS_TICK 1
+#endif
 
+#if HAS_TICK
 volatile AO_TICK_TYPE ao_tick_count;
 
 AO_TICK_TYPE
@@ -33,6 +41,7 @@ volatile __data uint8_t	ao_data_count;
 
 void stm_systick_isr(void)
 {
+	ao_validate_cur_stack();
 	if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
 		++ao_tick_count;
 #if HAS_TASK_QUEUE
@@ -42,11 +51,19 @@ void stm_systick_isr(void)
 #if AO_DATA_ALL
 		if (++ao_data_count == ao_data_interval) {
 			ao_data_count = 0;
-			ao_adc_poll();
+#if HAS_FAKE_FLIGHT
+			if (ao_fake_flight_active)
+				ao_fake_flight_poll();
+			else
+#endif
+				ao_adc_poll();
 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
 			ao_wakeup((void *) &ao_data_count);
 #endif
 		}
+#endif
+#ifdef AO_TIMER_HOOK
+		AO_TIMER_HOOK;
 #endif
 	}
 }
@@ -62,20 +79,6 @@ ao_timer_set_adc_interval(uint8_t interval)
 }
 #endif
 
-/*
- * According to the STM clock-configuration, timers run
- * twice as fast as the APB1 clock *if* the APB1 prescaler
- * is greater than 1.
- */
-
-#if AO_APB1_PRESCALER > 1
-#define TIMER_23467_SCALER 2
-#else
-#define TIMER_23467_SCALER 1
-#endif
-
-#define TIMER_10kHz	((AO_PCLK1 * TIMER_23467_SCALER) / 10000)
-
 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
 
 void
@@ -88,6 +91,8 @@ ao_timer_init(void)
 			   (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
 }
 
+#endif
+
 void
 ao_clock_init(void)
 {
@@ -97,7 +102,15 @@ ao_clock_init(void)
 	/* Switch to MSI while messing about */
 	stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
 	while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
-		asm("nop");
+		ao_arch_nop();
+
+	stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
+		(STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
+
+	/* wait for system to switch to MSI */
+	while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
+	       (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
+		ao_arch_nop();
 
 	/* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
 	stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
@@ -148,7 +161,6 @@ ao_clock_init(void)
 	stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
 
 	/* Enable 1 wait state so the CPU can run at 32MHz */
-	/* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
 	stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
 
 	/* Enable power interface clock */