X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstm%2Fao_timer.c;h=8b7c2327ff2bdd34f93e7f93a8351f0c3ff63a4f;hb=1e9b405e939136d25d937334d1f14f06c7d6127b;hp=78228e65b72d10ad43df98e47694fc92c4b374bf;hpb=5ed88fb72c3e3ecf3333c700d838667db71cfbdc;p=fw%2Faltos

diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index 78228e65..8b7c2327 100644
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -16,25 +16,14 @@
  */
 
 #include "ao.h"
+#include <ao_task.h>
 
-volatile __data AO_TICK_TYPE ao_tick_count;
+volatile AO_TICK_TYPE ao_tick_count;
 
-uint16_t ao_time(void)
+AO_TICK_TYPE
+ao_time(void)
 {
-	uint16_t	v;
-	ao_arch_critical(
-		v = ao_tick_count;
-		);
-	return v;
-}
-
-static __xdata uint8_t ao_forever;
-
-void
-ao_delay(uint16_t ticks)
-{
-	ao_alarm(ticks);
-	ao_sleep(&ao_forever);
+	return ao_tick_count;
 }
 
 #if AO_DATA_ALL
@@ -51,6 +40,10 @@ void stm_tim6_isr(void)
 	if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
 		stm_tim6.sr = 0;
 		++ao_tick_count;
+#if HAS_TASK_QUEUE
+		if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
+			ao_task_check_alarm((uint16_t) ao_tick_count);
+#endif
 #if AO_DATA_ALL
 		if (++ao_data_count == ao_data_interval) {
 			ao_data_count = 0;
@@ -65,10 +58,12 @@ void stm_tim6_isr(void)
 
 #if HAS_ADC
 void
-ao_timer_set_adc_interval(uint8_t interval) __critical
+ao_timer_set_adc_interval(uint8_t interval)
 {
-	ao_data_interval = interval;
-	ao_data_count = 0;
+	ao_arch_critical(
+		ao_data_interval = interval;
+		ao_data_count = 0;
+		);
 }
 #endif
 
@@ -96,7 +91,7 @@ ao_timer_init(void)
 	stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
 
 	stm_tim6.psc = TIMER_10kHz;
-	stm_tim6.arr = 100;
+	stm_tim6.arr = 99;
 	stm_tim6.cnt = 0;
 
 	/* Enable update interrupt */
@@ -275,6 +270,7 @@ ao_clock_init(void)
 	stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 
 
+#if DEBUG_THE_CLOCK
 	/* Output SYSCLK on PA8 for measurments */
 
 	stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
@@ -285,4 +281,5 @@ ao_clock_init(void)
 
 	stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
 	stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
+#endif
 }