X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.h;h=fbbb2b42ee196eaf9fced25891ff9c47266277c2;hb=89c3b1462b8c4b96e2071a87883aed5e030bbef9;hp=aeeaa85a4778e3eb7cc57e15a0a00bfbc6793b2f;hpb=729914652be34ad01933a703ae96064a0455d1a7;p=fw%2Fstlink diff --git a/src/stlink-common.h b/src/stlink-common.h index aeeaa85..fbbb2b4 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -103,13 +103,14 @@ extern "C" { #define STM32_CHIPID_F1_LOW 0x412 #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 - +#define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */ #define STM32_CHIPID_L1_MEDIUM 0x416 #define STM32_CHIPID_L0 0x417 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F4_HD 0x419 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420 +#define STM32_CHIPID_F446 0x421 #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F4_LP 0x423 @@ -117,11 +118,15 @@ extern "C" { #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 #define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_L1_CAT2 0x429 #define STM32_CHIPID_F1_XL 0x430 #define STM32_CHIPID_F37x 0x432 #define STM32_CHIPID_F4_DE 0x433 +#define STM32_CHIPID_F4_DE 0x433 + +#define STM32_CHIPID_F4_DSI 0x434 #define STM32_CHIPID_L1_HIGH 0x436 #define STM32_CHIPID_L152_RE 0x437 @@ -129,13 +134,17 @@ extern "C" { #define STM32_CHIPID_F3_SMALL 0x439 #define STM32_CHIPID_F0 0x440 - +#define STM32_CHIPID_F09X 0x442 #define STM32_CHIPID_F0_SMALL 0x444 #define STM32_CHIPID_F04 0x445 +#define STM32_CHIPID_F303_HIGH 0x446 + #define STM32_CHIPID_F0_CAN 0x448 +#define STM32_CHIPID_F7 0x449 + /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- @@ -170,6 +179,16 @@ extern "C" { // These maps are from a combination of the Programming Manuals, and // also the Reference manuals. (flash size reg is normally in ref man) static const chip_params_t devices[] = { + { + //RM0385 and DS10916 document was used to find these paramaters + .chip_id = STM32_CHIPID_F7, + .description = "F7 device", + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + }, { // table 2, PM0063 .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", @@ -206,6 +225,15 @@ extern "C" { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F4_DSI, + .description = "F46x and F47x device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F4_HD, .description = "F42x and F43x device", @@ -262,6 +290,15 @@ extern "C" { .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000 }, + { + .chip_id = STM32_CHIPID_L1_CAT2, + .description = "L1 Cat.2 device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", @@ -307,6 +344,16 @@ extern "C" { .bootrom_base = 0x1ffff000, .bootrom_size = 0x800 }, + { + // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + .chip_id = STM32_CHIPID_F446, + .description = "F446 device", + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. // Support based on DM00043574.pdf (RM0316) document. @@ -369,6 +416,15 @@ extern "C" { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, + { + .chip_id = STM32_CHIPID_F09X, + .description = "F09X device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters @@ -376,7 +432,7 @@ extern "C" { .description = "F04x device", .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, @@ -423,6 +479,31 @@ extern "C" { .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000 }, + { + // This is STK32F303RET6 device from STM32 F3 Nucelo board. + // Support based on DM00043574.pdf (RM0316) document rev 5. + .chip_id = STM32_CHIPID_F303_HIGH, + .description = "F303 high density device", + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000 + }, + { + // STM32L4x6 + // From RM0351. + .chip_id = STM32_CHIPID_L4, + .description = "L4 device", + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, }; @@ -485,7 +566,7 @@ extern "C" { void (*run) (stlink_t * stl); void (*status) (stlink_t * stl); void (*version) (stlink_t *sl); - uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr); + void (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); @@ -549,13 +630,13 @@ extern "C" { void stlink_exit_debug_mode(stlink_t *sl); void stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); - uint32_t stlink_core_id(stlink_t *sl); + void stlink_core_id(stlink_t *sl); void stlink_reset(stlink_t *sl); void stlink_jtag_reset(stlink_t *sl, int value); void stlink_run(stlink_t *sl); void stlink_status(stlink_t *sl); void stlink_version(stlink_t *sl); - uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr); + void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); @@ -574,7 +655,7 @@ extern "C" { // unprocessed int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length); + int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);