X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.h;h=a0bd64909d5b4f6fd9a7c7e22fb2880cca35fe78;hb=def6fc457d77475e9ff190105d372639f5808a77;hp=a25ca43847aaa556559b6a8f7b8b65a537fef050;hpb=fdfb82b53ca44d389cb2666cb557996203ed9093;p=fw%2Fstlink

diff --git a/src/stlink-common.h b/src/stlink-common.h
index a25ca43..a0bd649 100644
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -103,13 +103,14 @@ extern "C" {
 #define STM32_CHIPID_F1_LOW         0x412
 #define STM32_CHIPID_F4             0x413
 #define STM32_CHIPID_F1_HIGH        0x414
-
+#define STM32_CHIPID_L4             0x415       /* Seen on L4x6 (RM0351) */
 #define STM32_CHIPID_L1_MEDIUM      0x416
 #define STM32_CHIPID_L0             0x417
 #define STM32_CHIPID_F1_CONN        0x418
 #define STM32_CHIPID_F4_HD          0x419
 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
 
+#define STM32_CHIPID_F446           0x421
 #define STM32_CHIPID_F3             0x422
 #define STM32_CHIPID_F4_LP          0x423
 
@@ -123,6 +124,9 @@ extern "C" {
 
 #define STM32_CHIPID_F37x           0x432
 #define STM32_CHIPID_F4_DE          0x433
+#define STM32_CHIPID_F4_DE          0x433
+
+#define STM32_CHIPID_F4_DSI         0x434
 
 #define STM32_CHIPID_L1_HIGH        0x436
 #define STM32_CHIPID_L152_RE        0x437
@@ -139,6 +143,8 @@ extern "C" {
 
 #define STM32_CHIPID_F0_CAN         0x448
 
+#define STM32_CHIPID_F7             0x449
+
     /*
      * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
      * and some that are called "High".  0x427 is assigned to the other "Medium-
@@ -173,6 +179,16 @@ extern "C" {
     // These maps are from a combination of the Programming Manuals, and
     // also the Reference manuals.  (flash size reg is normally in ref man)
     static const chip_params_t devices[] = {
+        {
+            //RM0385 and DS10916 document was used to find these paramaters
+            .chip_id = STM32_CHIPID_F7,
+            .description = "F7 device",
+            .flash_size_reg = 0x1ff0f442,      // section 41.2
+            .flash_pagesize = 0x800,           // No flash pages
+            .sram_size = 0x50000,              // "SRAM" byte size in hex from DS Fig 18
+            .bootrom_base = 0x00100000,        // "System memory" starting address from DS Fig 18
+            .bootrom_size = 0xEDC0             // "System memory" byte size in hex from DS Fig 18
+        },
         { // table 2, PM0063
             .chip_id = STM32_CHIPID_F1_MEDIUM,
             .description = "F1 Medium-density device",
@@ -209,6 +225,15 @@ extern "C" {
             .bootrom_base = 0x1fff0000,
             .bootrom_size = 0x7800
         },
+        {
+            .chip_id = STM32_CHIPID_F4_DSI,
+            .description = "F46x and F47x device",
+            .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
+            .flash_pagesize = 0x4000,
+            .sram_size = 0x40000,
+            .bootrom_base = 0x1fff0000,
+            .bootrom_size = 0x7800
+        },
         {
             .chip_id = STM32_CHIPID_F4_HD,
             .description = "F42x and F43x device",
@@ -319,6 +344,16 @@ extern "C" {
             .bootrom_base = 0x1ffff000,
             .bootrom_size = 0x800
         },
+        {
+            // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
+            .chip_id = STM32_CHIPID_F446,
+            .description = "F446 device",
+            .flash_size_reg = 0x1fff7a22,
+            .flash_pagesize = 0x20000,
+            .sram_size = 0x20000,
+            .bootrom_base = 0x1fff0000,
+            .bootrom_size = 0x7800
+        },
         {
             // This is STK32F303VCT6 device from STM32 F3 Discovery board.
             // Support based on DM00043574.pdf (RM0316) document.
@@ -455,6 +490,20 @@ extern "C" {
             .bootrom_base = 0x1fffd800,      // 3.3.2 / Table 4 System Memory
             .bootrom_size = 0x2000
         },
+        {
+            // STM32L4x6
+            // From RM0351.
+            .chip_id = STM32_CHIPID_L4,
+            .description = "L4 device",
+            .flash_size_reg = 0x1fff75e0,    // "Flash size data register" (sec 45.2, page 1671)
+            .flash_pagesize = 0x800,         // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
+            // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
+            // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
+            // sizes; table 2, page 74 for SRAM2 location)
+            .sram_size = 0x18000,
+            .bootrom_base = 0x1fff0000,      // Tables 4-6, pages 80-81 (Bank 1 system memory)
+            .bootrom_size = 0x7000           // 28k (per bank), same source as base
+        },
 
  };