X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.h;h=579622892b38ccb4858a50636f454f0537003663;hb=3652f98a5d6c8bbe4707c5764b10e5bb9a13c370;hp=1d9e3878136abf39be00350c80a9342aa60935e5;hpb=5e1e150d5cced4770aae0f8e053c99d7d6a0d39c;p=fw%2Fstlink diff --git a/src/stlink-common.h b/src/stlink-common.h index 1d9e387..5796228 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -34,6 +34,7 @@ extern "C" { #define STLINK_GET_VERSION 0xf1 #define STLINK_GET_CURRENT_MODE 0xf5 +#define STLINK_GET_TARGET_VOLTAGE 0xF7 #define STLINK_DEBUG_COMMAND 0xF2 #define STLINK_DFU_COMMAND 0xF3 @@ -70,6 +71,10 @@ extern "C" { // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD +#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 +#define STLINK_JTAG_READDEBUG_32BIT 0x36 +#define STLINK_JTAG_DRIVE_NRST 0x3c +#define STLINK_JTAG_DRIVE_NRST 0x3c // cortex m3 technical reference manual #define CM3_REG_CPUID 0xE000ED00 @@ -77,31 +82,262 @@ extern "C" { #define CM3_REG_FP_COMP0 0xE0002008 /* cortex core ids */ + // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 +#define STM32F3_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 +#define STM32F0_CORE_ID 0xbb11477 +#define CORE_M3_R1 0x1BA00477 +#define CORE_M3_R2 0x4BA00477 +#define CORE_M4_R0 0x2BA01477 /* * Chip IDs are explained in the appropriate programming manual for the * DBGMCU_IDCODE register (0xE0042000) */ -#define CORE_M3_R1 0x1BA00477 -#define CORE_M3_R2 0x4BA00477 -#define CORE_M4_R0 0x2BA01477 +// stm32 chipids, only lower 12 bits.. +#define STM32_CHIPID_F1_MEDIUM 0x410 +#define STM32_CHIPID_F2 0x411 +#define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F3 0x422 +#define STM32_CHIPID_F37x 0x432 +#define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F4_HD 0x419 +#define STM32_CHIPID_F4_LP 0x423 +#define STM32_CHIPID_F1_HIGH 0x414 +#define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 +/* + * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" + * and some that are called "High". 0x427 is assigned to the other "Medium- + * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and + * 0x436 HIGH. + */ +#define STM32_CHIPID_L1_HIGH 0x436 +#define STM32_CHIPID_F1_CONN 0x418 +#define STM32_CHIPID_F1_VL_MEDIUM 0x420 +#define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_F1_XL 0x430 +#define STM32_CHIPID_F0 0x440 +#define STM32_CHIPID_F0_SMALL 0x444 + +// Constant STM32 memory map figures +#define STM32_FLASH_BASE 0x08000000 +#define STM32_SRAM_BASE 0x20000000 -/* using chip id for F4 ident, since core id is same as F1 */ -#define STM32F4_CHIP_ID 0x413 +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define DHCSR 0xe000edf0 +#define DCRSR 0xe000edf4 +#define DCRDR 0xe000edf8 +#define DBGKEY 0xa05f0000 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + typedef struct chip_params_ { + uint32_t chip_id; + char* description; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base, bootrom_size; + } chip_params_t; + + +// These maps are from a combination of the Programming Manuals, and +// also the Reference manuals. (flash size reg is normally in ref man) +static const chip_params_t devices[] = { + { // table 2, PM0063 + .chip_id = STM32_CHIPID_F1_MEDIUM, + .description = "F1 Medium-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = STM32_CHIPID_F2, + .description = "F2 device", + .flash_size_reg = 0x1ff7a22, /* RM0033 sind Rev 4*/ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { // PM0063 + .chip_id = STM32_CHIPID_F1_LOW, + .description = "F1 Low-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STM32_CHIPID_F4, + .description = "F4 device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STM32_CHIPID_F4_HD, + .description = "F42x and F43x device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STM32_CHIPID_F4_LP, + .description = "F4 device (low power)", + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STM32_CHIPID_F1_HIGH, + .description = "F1 High-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = STM32_CHIPID_L1_MEDIUM, + .description = "L1 Med-density device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, + .description = "L1 Medium-Plus-density device", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STM32_CHIPID_L1_HIGH, + .description = "L1 High-density device", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + + { + .chip_id = STM32_CHIPID_F1_CONN, + .description = "F1 Connectivity line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { + .chip_id = STM32_CHIPID_F1_VL_MEDIUM, + .description = "F1 Medium-density Value Line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. + .chip_id = STM32_CHIPID_F3, + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) + .chip_id = STM32_CHIPID_F37x, + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STM32_CHIPID_F1_VL_HIGH, + .description = "F1 High-density value line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STM32_CHIPID_F1_XL, + .description = "F1 XL-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F0, + .description = "F0 device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F0_SMALL, + .description = "F0 small device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + }; + + typedef struct { uint32_t r[16]; + uint32_t s[32]; uint32_t xpsr; uint32_t main_sp; uint32_t process_sp; uint32_t rw; uint32_t rw2; + uint8_t control; + uint8_t faultmask; + uint8_t basepri; + uint8_t primask; + uint32_t fpscr; } reg; typedef uint32_t stm32_addr_t; @@ -143,18 +379,25 @@ extern "C" { void (*exit_dfu_mode) (stlink_t * stl); void (*core_id) (stlink_t * stl); void (*reset) (stlink_t * stl); + void (*jtag_reset) (stlink_t * stl, int value); void (*run) (stlink_t * stl); void (*status) (stlink_t * stl); void (*version) (stlink_t *sl); + uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr); void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); void (*read_all_regs) (stlink_t *sl, reg * regp); void (*read_reg) (stlink_t *sl, int r_idx, reg * regp); + void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); + void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); + void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); void (*write_reg) (stlink_t *sl, uint32_t reg, int idx); void (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); void (*force_debug) (stlink_t *sl); + int32_t (*target_voltage) (stlink_t *sl); } stlink_backend_t; struct _stlink { @@ -170,14 +413,9 @@ extern "C" { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; uint32_t core_id; - uint16_t chip_id; + uint32_t chip_id; int core_stat; - - - /* medium density stm32 flash settings */ -#define STM32_FLASH_BASE 0x08000000 -#define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 @@ -188,25 +426,19 @@ extern "C" { size_t flash_size; size_t flash_pgsz; - /* in flash system memory */ -#define STM32_SYSTEM_BASE 0x1ffff000 -#define STM32_SYSTEM_SIZE (2 * 1024) - stm32_addr_t sys_base; - size_t sys_size; - /* sram settings */ -#define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) #define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; + + // bootloader + stm32_addr_t sys_base; + size_t sys_size; + struct stlink_version_ version; }; - // some quick and dirty logging... - void D(stlink_t *sl, char *txt); - void DD(stlink_t *sl, char *format, ...); - //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); // delegated functions... @@ -216,29 +448,37 @@ extern "C" { void stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); uint32_t stlink_core_id(stlink_t *sl); - void stlink_identify_device(stlink_t *sl); void stlink_reset(stlink_t *sl); + void stlink_jtag_reset(stlink_t *sl, int value); void stlink_run(stlink_t *sl); void stlink_status(stlink_t *sl); void stlink_version(stlink_t *sl); + uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr); void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_read_all_regs(stlink_t *sl, reg *regp); + void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); + void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); + void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp); void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); void stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); void stlink_force_debug(stlink_t *sl); + int stlink_target_voltage(stlink_t *sl); // unprocessed int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length); + int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); // PUBLIC - uint16_t stlink_chip_id(stlink_t *sl); + uint32_t stlink_chip_id(stlink_t *sl); void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); // privates, publics, the rest.... @@ -257,6 +497,7 @@ extern "C" { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + int stlink_load_device_params(stlink_t *sl);