X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.h;h=2230dca8352ff0727ef0b84d159df4c680a45da4;hb=b998bdd9857f7b66452282806e725c4a1073e607;hp=2fe04e188f3830ae0f3e5026955ae6b62318fcde;hpb=5a379699bb2d0e282dcd74122e94e1377198cd95;p=fw%2Fstlink

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 2fe04e1..2230dca 100644
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -81,6 +81,17 @@ extern "C" {
 #define STM32L_CORE_ID 0x2ba01477
 #define STM32F4_CORE_ID 0x2ba01477
 
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/* using chip id for F4 ident, since core id is same as F1 */
+#define STM32F4_CHIP_ID 0x413
+
 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
 #define C_BUF_LEN 32
 
@@ -159,6 +170,7 @@ extern "C" {
         // transport layer verboseness: 0 for no debug info, 10 for lots
         int verbose;
         uint32_t core_id;
+        uint16_t chip_id;
         int core_stat;
 
 
@@ -168,6 +180,10 @@ extern "C" {
 #define STM32_FLASH_SIZE (128 * 1024)
 #define STM32_FLASH_PGSZ 1024
 #define STM32L_FLASH_PGSZ 256
+
+#define STM32F4_FLASH_PGSZ 16384
+#define STM32F4_FLASH_SIZE (128 * 1024 * 8)
+
         stm32_addr_t flash_base;
         size_t flash_size;
         size_t flash_pgsz;
@@ -200,6 +216,7 @@ extern "C" {
     void stlink_exit_dfu_mode(stlink_t *sl);
     void stlink_close(stlink_t *sl);
     uint32_t stlink_core_id(stlink_t *sl);
+    void stlink_identify_device(stlink_t *sl);
     void stlink_reset(stlink_t *sl);
     void stlink_run(stlink_t *sl);
     void stlink_status(stlink_t *sl);