X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.h;h=2230dca8352ff0727ef0b84d159df4c680a45da4;hb=93b186f15b493728d1662f4a6f96aae835962f02;hp=3e5d461fe154c2b41de6c955986608378e658d1d;hpb=8f4e7c64dc798e6c5471cb6844f08f5b35f1e4bf;p=fw%2Fstlink

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 3e5d461..2230dca 100644
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -18,11 +18,12 @@ extern "C" {
     // Max data transfer size.
     // 6kB = max mem32_read block, 8kB sram
     //#define Q_BUF_LEN	96
-#define Q_BUF_LEN	1024 * 100
+#define Q_BUF_LEN			(1024 * 100)
 
     // st-link vendor cmd's
 #define USB_ST_VID			0x0483
 #define USB_STLINK_PID			0x3744
+#define USB_STLINK_32L_PID		0x3748
 
     // STLINK_DEBUG_RESETSYS, etc:
 #define STLINK_OK			0x80
@@ -37,6 +38,7 @@ extern "C" {
 #define STLINK_DEBUG_COMMAND		0xF2
 #define STLINK_DFU_COMMAND		0xF3
 #define STLINK_DFU_EXIT		0x07
+    // enter dfu could be 0x08?
 
     // STLINK_GET_CURRENT_MODE
 #define STLINK_DEV_DFU_MODE		0x00
@@ -64,6 +66,34 @@ extern "C" {
 #define STLINK_DEBUG_WRITEDEBUGREG	0x0f
 #define STLINK_DEBUG_ENTER_SWD		0xa3
 #define STLINK_DEBUG_ENTER_JTAG	0x00
+    
+    // TODO - possible poor names...
+#define STLINK_SWD_ENTER 0x30
+#define STLINK_SWD_READCOREID 0x32  // TBD
+
+// cortex m3 technical reference manual
+#define CM3_REG_CPUID 0xE000ED00
+#define CM3_REG_FP_CTRL 0xE0002000
+#define CM3_REG_FP_COMP0 0xE0002008
+
+/* cortex core ids */
+#define STM32VL_CORE_ID 0x1ba01477
+#define STM32L_CORE_ID 0x2ba01477
+#define STM32F4_CORE_ID 0x2ba01477
+
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/* using chip id for F4 ident, since core id is same as F1 */
+#define STM32F4_CHIP_ID 0x413
+
+/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
+#define C_BUF_LEN 32
 
     typedef struct {
         uint32_t r[16];
@@ -75,6 +105,21 @@ extern "C" {
     } reg;
 
     typedef uint32_t stm32_addr_t;
+    
+    typedef struct _cortex_m3_cpuid_ {
+        uint16_t implementer_id;
+        uint16_t variant;
+        uint16_t part;
+        uint8_t revision;
+    } cortex_m3_cpuid_t;
+
+    typedef struct stlink_version_ {
+        uint32_t stlink_v;
+        uint32_t jtag_v;
+        uint32_t swim_v;
+        uint32_t st_vid;
+        uint32_t stlink_pid;
+    } stlink_version_t;
 
     typedef struct flash_loader {
         stm32_addr_t loader_addr; /* loader sram adddr */
@@ -100,21 +145,24 @@ extern "C" {
         void (*reset) (stlink_t * stl);
         void (*run) (stlink_t * stl);
         void (*status) (stlink_t * stl);
-        void (*version) (stlink_t * stl);
+        void (*version) (stlink_t *sl);
         void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
-        void (*read_all_regs) (stlink_t *sl, reg* regp);
-        void (*read_reg) (stlink_t *sl, int r_idx, reg* regp);
+        void (*read_all_regs) (stlink_t *sl, reg * regp);
+        void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
         void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
         void (*step) (stlink_t * stl);
         int (*current_mode) (stlink_t * stl);
+        void (*force_debug) (stlink_t *sl);
     } stlink_backend_t;
 
     struct _stlink {
         struct _stlink_backend *backend;
         void *backend_data;
 
+        // Room for the command header
+        unsigned char c_buf[C_BUF_LEN];
         // Data transferred from or to device
         unsigned char q_buf[Q_BUF_LEN];
         int q_len;
@@ -122,6 +170,7 @@ extern "C" {
         // transport layer verboseness: 0 for no debug info, 10 for lots
         int verbose;
         uint32_t core_id;
+        uint16_t chip_id;
         int core_stat;
 
 
@@ -130,6 +179,11 @@ extern "C" {
 #define STM32_FLASH_BASE 0x08000000
 #define STM32_FLASH_SIZE (128 * 1024)
 #define STM32_FLASH_PGSZ 1024
+#define STM32L_FLASH_PGSZ 256
+
+#define STM32F4_FLASH_PGSZ 16384
+#define STM32F4_FLASH_SIZE (128 * 1024 * 8)
+
         stm32_addr_t flash_base;
         size_t flash_size;
         size_t flash_pgsz;
@@ -143,6 +197,7 @@ extern "C" {
         /* sram settings */
 #define STM32_SRAM_BASE 0x20000000
 #define STM32_SRAM_SIZE (8 * 1024)
+#define STM32L_SRAM_SIZE (16 * 1024)
         stm32_addr_t sram_base;
         size_t sram_size;
 
@@ -160,7 +215,8 @@ extern "C" {
     void stlink_exit_debug_mode(stlink_t *sl);
     void stlink_exit_dfu_mode(stlink_t *sl);
     void stlink_close(stlink_t *sl);
-    void stlink_core_id(stlink_t *sl);
+    uint32_t stlink_core_id(stlink_t *sl);
+    void stlink_identify_device(stlink_t *sl);
     void stlink_reset(stlink_t *sl);
     void stlink_run(stlink_t *sl);
     void stlink_status(stlink_t *sl);
@@ -173,13 +229,17 @@ extern "C" {
     void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
     void stlink_step(stlink_t *sl);
     int stlink_current_mode(stlink_t *sl);
+    void stlink_force_debug(stlink_t *sl);
 
 
     // unprocessed
-    void stlink_force_debug(stlink_t *sl);
-
     int stlink_erase_flash_mass(stlink_t* sl);
     int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
+    int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
+    
+    // PUBLIC
+    uint16_t stlink_chip_id(stlink_t *sl);
+    void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
 
     // privates, publics, the rest....
     // TODO sort what is private, and what is not