X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=fac7b685c225cdcab25739bdadfc44ee2254001d;hb=6f194ad388fedf287a6200ea7efb16c4118ca4c1;hp=fcdb405ff84d65cb6478e08455a9d01c605c7ba7;hpb=0ff09f90ce176d0700eb88ec1ee1ec3932978c73;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index fcdb405..fac7b68 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1,4 +1,4 @@ - +#define DEBUG_FLASH 0 #include #include @@ -13,26 +13,18 @@ #include "stlink-common.h" +#include "uglylogging.h" -void D(stlink_t *sl, char *txt) { - if (sl->verbose > 1) - fputs(txt, stderr); -} - -void DD(stlink_t *sl, char *format, ...) { - if (sl->verbose > 0) { - va_list list; - va_start(list, format); - vfprintf(stderr, format, list); - va_end(list); - } -} - +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ - +// TODO - all of this needs to be abstracted out.... #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -129,27 +121,27 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return (*(uint32_t*) sl->q_buf) & 0xff; + return stlink_read_debug32(sl, FLASH_WRPR) & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_WRPR); } static inline uint32_t read_flash_obr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_OBR); } static inline uint32_t read_flash_cr(stlink_t *sl) { + uint32_t res; if(sl->chip_id==STM32F4_CHIP_ID) - stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_F4_CR); else - stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t)); - fprintf(stdout, "CR:%X\n", *(uint32_t*) sl->q_buf); - return *(uint32_t*) sl->q_buf; + res = stlink_read_debug32(sl, FLASH_CR); +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return res; } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -167,16 +159,12 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if(sl->chip_id==STM32F4_CHIP_ID) { - write_uint32(sl->q_buf, FLASH_KEY1); - stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t)); - write_uint32(sl->q_buf, FLASH_KEY2); - stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { - write_uint32(sl->q_buf, FLASH_KEY1); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); - write_uint32(sl->q_buf, FLASH_KEY2); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); } } @@ -186,24 +174,24 @@ static int unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); - if (is_flash_locked(sl)) + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); return -1; + } } - + ILOG("Successfully unlocked flash\n"); return 0; } static void lock_flash(stlink_t *sl) { if(sl->chip_id==STM32F4_CHIP_ID) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, n); } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } @@ -212,47 +200,40 @@ static void set_flash_cr_pg(stlink_t *sl) { if(sl->chip_id==STM32F4_CHIP_ID) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } else { const uint32_t n = 1 << FLASH_CR_PG; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - write_uint32(sl->q_buf, n); if(sl->chip_id==STM32F4_CHIP_ID) - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, n); else - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_per(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_PER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_mer(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_MER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_strt(stlink_t *sl) { @@ -260,29 +241,27 @@ static void set_flash_cr_strt(stlink_t *sl) { { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } else { /* assume come on the flash_cr_per path */ const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } static inline uint32_t read_flash_acr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_ACR); } static inline uint32_t read_flash_sr(stlink_t *sl) { + uint32_t res; if(sl->chip_id==STM32F4_CHIP_ID) - stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_F4_SR); else - stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t)); - //fprintf(stdout, "SR:%X\n", *(uint32_t*) sl->q_buf); - return *(uint32_t*) sl->q_buf; + res = stlink_read_debug32(sl, FLASH_SR); + //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { @@ -304,8 +283,7 @@ static inline unsigned int is_flash_eop(stlink_t *sl) { static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_SR, n); } static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { @@ -315,17 +293,17 @@ static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { } static inline void write_flash_ar(stlink_t *sl, uint32_t n) { - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_AR, n); } static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { uint32_t x = read_flash_cr(sl); x &= ~(0x03 << 8); x |= (n << 8); - fprintf(stdout, "PSIZ:%X %X\n", x, n); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, FLASH_F4_CR, x); } @@ -334,9 +312,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { x &= ~FLASH_F4_CR_SNB_MASK; x |= (n << FLASH_F4_CR_SNB); x |= (1 << FLASH_F4_CR_SER); - fprintf(stdout, "SNB:%X %X\n", x, n); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, FLASH_F4_CR, x); } #if 0 /* todo */ @@ -352,52 +331,45 @@ static void disable_flash_read_protection(stlink_t *sl) { // Delegates to the backends... void stlink_close(stlink_t *sl) { - D(sl, "\n*** stlink_close ***\n"); + DLOG("*** stlink_close ***\n"); sl->backend->close(sl); free(sl); } void stlink_exit_debug_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_debug_mode ***\n"); + DLOG("*** stlink_exit_debug_mode ***\n"); + stlink_write_debug32(sl, DHCSR, DBGKEY); sl->backend->exit_debug_mode(sl); } void stlink_enter_swd_mode(stlink_t *sl) { - D(sl, "\n*** stlink_enter_swd_mode ***\n"); + DLOG("*** stlink_enter_swd_mode ***\n"); sl->backend->enter_swd_mode(sl); } // Force the core into the debug mode -> halted state. void stlink_force_debug(stlink_t *sl) { - D(sl, "\n*** stlink_force_debug_mode ***\n"); + DLOG("*** stlink_force_debug_mode ***\n"); sl->backend->force_debug(sl); } void stlink_exit_dfu_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_dfu_mode ***\n"); + DLOG("*** stlink_exit_dfu_mode ***\n"); sl->backend->exit_dfu_mode(sl); } uint32_t stlink_core_id(stlink_t *sl) { - D(sl, "\n*** stlink_core_id ***\n"); + DLOG("*** stlink_core_id ***\n"); sl->backend->core_id(sl); if (sl->verbose > 2) stlink_print_data(sl); + DLOG("core_id = 0x%08x\n", sl->core_id); return sl->core_id; } -void stlink_identify_device(stlink_t *sl) { - uint32_t core_id=stlink_core_id(sl); - stlink_read_mem32(sl, 0xE0042000, 4); - uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) | - (sl->q_buf[3] << 24); - /* Fix chip_id for F4 */ - if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { - printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); - chip_id = 0x413; - } - sl->chip_id=chip_id; - sl->core_id=core_id; +uint32_t stlink_chip_id(stlink_t *sl) { + uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); + return chip_id; } /** @@ -406,8 +378,7 @@ void stlink_identify_device(stlink_t *sl) { * @param cpuid pointer to the result object */ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - stlink_read_mem32(sl, CM3_REG_CPUID, 4); - uint32_t raw = read_uint32(sl->q_buf, 0); + uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; @@ -415,18 +386,78 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { return; } +/** + * reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + ILOG("Loading device parameters....\n"); + const chip_params_t *params = NULL; + + sl->core_id = stlink_core_id(sl); + uint32_t chip_id = stlink_chip_id(sl); + + /* Fix chip_id for F4 rev A errata */ + if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) { + chip_id = 0x413; + } + + sl->chip_id = chip_id; + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == (chip_id & 0xFFF)) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + WLOG("unknown chip id! %#x\n", chip_id); + return -1; + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + + // read flash size from hardware, if possible... + if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) { + sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID + } else { + uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; + sl->flash_size = flash_size * 1024; + } + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); + // TODO make note of variable page size here..... + ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); + return 0; +} + void stlink_reset(stlink_t *sl) { - D(sl, "\n*** stlink_reset ***\n"); + DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); } +void stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset ***\n"); + sl->backend->jtag_reset(sl, value); +} + void stlink_run(stlink_t *sl) { - D(sl, "\n*** stlink_run ***\n"); + DLOG("*** stlink_run ***\n"); sl->backend->run(sl); } void stlink_status(stlink_t *sl) { - D(sl, "\n*** stlink_status ***\n"); + DLOG("*** stlink_status ***\n"); sl->backend->status(sl); stlink_core_stat(sl); } @@ -457,26 +488,36 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { } void stlink_version(stlink_t *sl) { - D(sl, "*** looking up stlink version\n"); - stlink_version_t slv; + DLOG("*** looking up stlink version\n"); sl->backend->version(sl); - _parse_version(sl, &slv); + _parse_version(sl, &sl->version); - DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); - DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid); - DD(sl, "stlink version = 0x%x\n", slv.stlink_v); - DD(sl, "jtag version = 0x%x\n", slv.jtag_v); - DD(sl, "swim version = 0x%x\n", slv.swim_v); - if (slv.jtag_v == 0) { - DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n"); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); + if (sl->version.jtag_v == 0) { + DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); } - if (slv.swim_v == 0) { - DD(sl, " notice: the firmware doesn't support a swim interface\n"); + if (sl->version.swim_v == 0) { + DLOG(" notice: the firmware doesn't support a swim interface\n"); } } +uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { + uint32_t data = sl->backend->read_debug32(sl, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + return data; +} + +void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); + sl->backend->write_debug32(sl, addr, data); +} + void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem32 ***\n"); + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return; @@ -485,7 +526,7 @@ void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_read_mem32 ***\n"); + DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); @@ -495,23 +536,23 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem8 ***\n"); + DLOG("*** stlink_write_mem8 ***\n"); sl->backend->write_mem8(sl, addr, len); } void stlink_read_all_regs(stlink_t *sl, reg *regp) { - D(sl, "\n*** stlink_read_all_regs ***\n"); + DLOG("*** stlink_read_all_regs ***\n"); sl->backend->read_all_regs(sl, regp); } void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - D(sl, "\n*** stlink_write_reg\n"); + DLOG("*** stlink_write_reg\n"); sl->backend->write_reg(sl, reg, idx); } void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { - D(sl, "\n*** stlink_read_reg\n"); - DD(sl, " (%d) ***\n", r_idx); + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); @@ -528,7 +569,7 @@ unsigned int is_core_halted(stlink_t *sl) { } void stlink_step(stlink_t *sl) { - D(sl, "\n*** stlink_step ***\n"); + DLOG("*** stlink_step ***\n"); sl->backend->step(sl); } @@ -536,16 +577,16 @@ int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { case STLINK_DEV_DFU_MODE: - DD(sl, "stlink current mode: dfu\n"); + DLOG("stlink current mode: dfu\n"); return mode; case STLINK_DEV_DEBUG_MODE: - DD(sl, "stlink current mode: debug (jtag or swd)\n"); + DLOG("stlink current mode: debug (jtag or swd)\n"); return mode; case STLINK_DEV_MASS_MODE: - DD(sl, "stlink current mode: mass\n"); + DLOG("stlink current mode: mass\n"); return mode; } - DD(sl, "stlink mode: unknown!\n"); + DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; } @@ -596,11 +637,11 @@ void stlink_core_stat(stlink_t *sl) { switch (sl->q_buf[0]) { case STLINK_CORE_RUNNING: sl->core_stat = STLINK_CORE_RUNNING; - DD(sl, " core status: running\n"); + DLOG(" core status: running\n"); return; case STLINK_CORE_HALTED: sl->core_stat = STLINK_CORE_HALTED; - DD(sl, " core status: halted\n"); + DLOG(" core status: halted\n"); return; default: sl->core_stat = STLINK_CORE_STAT_UNKNOWN; @@ -609,7 +650,7 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < 2) + if (sl->q_len <= 0 || sl->verbose < UDEBUG) return; if (sl->verbose > 2) fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len); @@ -762,6 +803,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; + int num_zero = 0; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -773,6 +815,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) for (off = 0; off < size; off += 1024) { size_t read_size = 1024; size_t rounded_size; + size_t index; if ((off + read_size) > size) read_size = size - off; @@ -783,12 +826,21 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + off, rounded_size); + for(index = 0; index < read_size; index ++) { + if (sl->q_buf[index] == 0) + num_zero ++; + else + num_zero = 0; + } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); goto on_error; } } + /* Ignore NULL Bytes at end of file */ + ftruncate(fd, size - num_zero); + /* success */ error = 0; @@ -816,22 +868,25 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } -uint32_t calculate_sectorsize(stlink_t *sl, uint32_t flashaddr){ +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if(sl->chip_id == STM32F4_CHIP_ID) { uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector<4) return (0x4000); - else if(sector<5) return(0x10000); - else return(0x20000); + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; } - else return (sl->flash_pgsz); + return (sl->flash_pgsz); } -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) +/** + * Erase a page of flash, assumes sl is fully populated with things like chip/core ids + * @param sl stlink context + * @param flashaddr an address in the flash page to erase + * @return 0 on success -ve on failure + */ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - /* page an addr in the page to erase */ - - stlink_identify_device(sl); - + ILOG("Erasing flash page at addr: %#x\n", flashaddr); if (sl->chip_id == STM32F4_CHIP_ID) { /* wait for ongoing op to finish */ @@ -841,13 +896,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) unlock_flash_if(sl); /* select the page to erase */ - //Page is passed to us as an addr, so calculate the actual page - uint32_t addr=page; - - page=calculate_F4_sectornum(addr); + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); - fprintf(stderr, "Erasing Sector:%u SectorSize:%u\n", page, calculate_sectorsize(sl, addr)); - write_flash_cr_snb(sl, page); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); /* start erase operation */ set_flash_cr_strt(sl); @@ -858,55 +911,46 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* relock the flash */ //todo: fails to program if this is in lock_flash(sl); - fprintf(stdout, "Erase Final CR:%X\n", read_flash_cr(sl)); - +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); +#endif } - else if (sl->core_id == STM32L_CORE_ID) { uint32_t val; /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear (0x%x)\n", val); + WLOG("pecr.pelock not clear (%#x)\n", val); return -1; } /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear (0x%x)\n", val); + WLOG("pecr.prglock not clear (%#x)\n", val); return -1; } /* unused: unlock the option byte block */ #if 0 - write_uint32(sl->q_buf, 0xfbead9c8); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x24252627); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); /* check pecr.optlock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 2)) { fprintf(stderr, "pecr.prglock not clear\n"); @@ -916,25 +960,37 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* set pecr.{erase,prog} */ val |= (1 << 9) | (1 << 3); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - /* wait for sr.busy to be cleared */ - while (1) +#if 0 /* fix_to_be_confirmed */ + + /* wait for sr.busy to be cleared + MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + wrong and we do not need to wait here for clearing the busy bit. + TEXANE: ok, if experience says so and it works for you, we comment + it. If someone has a problem, please drop an email. + */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; } +#endif /* fix_to_be_confirmed */ + /* write 0 to the first word of the page to be erased */ - memset(sl->q_buf, 0, sizeof(uint32_t)); - stlink_write_mem32(sl, page, sizeof(uint32_t)); + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + { + } /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID) { @@ -948,7 +1004,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) set_flash_cr_per(sl); /* select the page to erase */ - write_flash_ar(sl, page); + write_flash_ar(sl, flashaddr); /* start erase operation, reset by hw with bsy bit */ set_flash_cr_strt(sl); @@ -961,7 +1017,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) } else { - fprintf(stderr, "unknown device!\n"); + WLOG("unknown coreid: %x\n", sl->core_id); return -1; } @@ -999,13 +1055,13 @@ int init_flash_loader(stlink_t *sl, flash_loader_t* fl) { /* allocate the loader in sram */ if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) { - fprintf(stderr, "write_loader_to_sram() == -1\n"); + WLOG("Failed to write flash loader to sram!\n"); return -1; } /* allocate a one page buffer in sram right after loader */ fl->buf_addr = fl->loader_addr + size; - + ILOG("Successfully loaded flash loader in sram\n"); return 0; } @@ -1068,7 +1124,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1098,43 +1154,83 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return res; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - flash_loader_t fl; + if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); + return 0; + } + ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += sl->flash_pgsz) { + size_t aligned_size; - stlink_identify_device(sl); + /* adjust last page size */ + size_t cmp_size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > length) + cmp_size = length - off; -#if 0 /* todo: use in debugging mode only */ - fprintf(stdout, "WriteFlash - addr:%x len:%x\n", addr, len); - fprintf(stdout, "CoreID:%X ChipID:%X\n", sl->core_id, sl->chip_id); -#endif + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); + stlink_read_mem32(sl, address + off, aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + WLOG("Verification of flash failed at offset: %zd\n", off); + return -1; + } + } + ILOG("Flash written and verified! jolly good!\n"); + return 0; + +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { + size_t off; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", + len, len, addr, addr); /* check addr range is inside the flash */ + stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { - fprintf(stderr, "addr too low\n"); + WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; } else if ((addr + len) < addr) { - fprintf(stderr, "addr overruns\n"); + WLOG("addr overruns\n"); return -1; } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - fprintf(stderr, "addr too high\n"); + WLOG("addr too high\n"); return -1; } else if ((addr & 1) || (len & 1)) { - fprintf(stderr, "unaligned addr or size\n"); + WLOG("unaligned addr or size\n"); return -1; } else if (addr & (sl->flash_pgsz - 1)) { - fprintf(stderr, "addr not a multiple of pagesize, not supported\n"); + WLOG("addr not a multiple of pagesize, not supported\n"); return -1; } + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); /* erase each page */ - for (off = 0; off < len; off += calculate_sectorsize(sl, addr + off) ) { + int page_count = 0; + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { - fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off); - return -1; + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + return -1; } + page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); if (sl->chip_id == STM32F4_CHIP_ID) { /* todo: check write operation */ @@ -1151,6 +1247,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #define PROGRESS_CHUNK_SIZE 0x1000 /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; if (sl->verbose >= 1) { if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { /* show progress. writing procedure is slow @@ -1161,8 +1258,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t)); - stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ wait_flash_busy(sl); @@ -1172,7 +1269,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned lock_flash(sl); #if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:%X\n", read_flash_cr(sl)); + fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); #endif @@ -1181,7 +1278,6 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned else if (sl->core_id == STM32L_CORE_ID) { /* use fast word write. todo: half page. */ - uint32_t val; #if 0 /* todo: check write operation */ @@ -1193,28 +1289,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check write operation */ /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); return -1; } /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; @@ -1222,6 +1312,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; if (sl->verbose >= 1) { if ((off & (sl->flash_pgsz - 1)) == 0) { /* show progress. writing procedure is slow @@ -1232,20 +1323,18 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t)); - stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while (1) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { } #if 0 /* todo: check redo write operation */ /* check written bytes. todo: should be on a per page basis. */ - stlink_read_mem32(sl, addr + off, sizeof(uint32_t)); - if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) { + data = stlink_read_debug32(sl, addr + off); + if (data == *(uint32_t*)(base + off)) { /* re erase the page and redo the write operation */ uint32_t page; uint32_t val; @@ -1262,14 +1351,13 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); page = addr + off; - fprintf(stderr, "invalid write @%x(%x): %x != %x. retrying.\n", + fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); stlink_erase_flash_page(sl, page); @@ -1282,105 +1370,74 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check redo write operation */ } /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - } - - - + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + } else if (sl->core_id == STM32VL_CORE_ID) { + ILOG("Starting Flash write for VL core id\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } - else if (sl->core_id == STM32VL_CORE_ID) { - /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - fprintf(stderr, "init_flash_loader() == -1\n"); - return -1; - } - /* write each page. above WRITE_BLOCK_SIZE fails? */ + /* write each page. above WRITE_BLOCK_SIZE fails? */ #define WRITE_BLOCK_SIZE 0x40 - for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { - /* adjust last write size */ - size_t size = WRITE_BLOCK_SIZE; - if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; - - /* unlock and set programming mode */ - unlock_flash_if(sl); - set_flash_cr_pg(sl); - - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off); - return -1; - } - lock_flash(sl); - } - } - - - - - else - { - fprintf(stderr, "unknown device!\n"); - return -1; - } - - - - - -#if(0) - //todo: F4 Can't stlink_read_mem32 an entire sector, not enough ram! - for (off = 0; off < len; off += sl->flash_pgsz) { - size_t aligned_size; - - /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) - cmp_size = len - off; - - aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - - fprintf(stdout, "AlignedSize:%x\n", aligned_size); - stlink_read_mem32(sl, addr + off, aligned_size); - - if (memcmp(sl->q_buf, base + off, cmp_size)) - return -1; + int write_block_count = 0; + for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { + ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count, + WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE); + /* adjust last write size */ + size_t size = WRITE_BLOCK_SIZE; + if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; + + /* unlock and set programming mode */ + unlock_flash_if(sl); + set_flash_cr_pg(sl); + //DLOG("Finished setting flash cr pg, running loader!\n"); + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } + lock_flash(sl); + DLOG("Finished writing block %d\n", write_block_count++); + } + } else { + WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return -1; } -#endif - - return 0; + + return stlink_verify_write_flash(sl, addr, base, len); } - - - +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ - int err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); + WLOG("map_file() == -1\n"); return -1; } - err = stlink_write_flash(sl, addr, mf.base, mf.len); - unmap_file(&mf); - return err; } int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); + // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - fprintf(stderr, "write_buffer_to_sram() == -1\n"); + // IMPOSSIBLE! + WLOG("write_buffer_to_sram() == -1\n"); return -1; } @@ -1409,12 +1466,12 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; } /* run loader */ - stlink_step(sl); + stlink_run(sl); /* wait until done (reaches breakpoint) */ while (is_core_halted(sl) == 0) ; @@ -1441,7 +1498,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; }